Scott E. Thompson

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.

A logic nanotechnology featuring strained-silicon

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.

Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

Summary form only given. We investigate scaling challenges and outline device design requirements needed to support high performance-low power planar CMOS transistor structures with physical gate lengths (L/sub GATE/) below 50 nm. This work uses a combination of simulation results, experimental data and critical analysis of published data. A realistic assessment of gate oxide thickness scaling and maximum tolerable oxide leakage is provided. We conclude that the commonly accepted upper limit of 1 A/cm/sup 2/ for gate leakage is overly pessimistic and that leakage values of up to 100 A/cm/sup 2/ are deemed acceptable for future logic technology generations. Unique channel mobility and junction edge leakage degradation mechanisms, which become prominent at 50 nm L/sub GATE/ dimensions, are highlighted using quantitative analysis. Source-drain extension (SDE) profile design requirements to simultaneously minimize short channel effects (SCE) and achieve low parasitic resistance for sub-50 nm L/sub GATE/ transistors are described for the first time.

Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

We describe the device physics of uniaxial strained silicon transistors. Uniaxial strain is more effective, less costly and easier to implement. The highest PMOS drive current to date is reported: 0.72mA/ /spl mu/m. Pattern sensitivity and mobility/Rext partitioning are discussed. Finally we measure inverter delays as low as 4.6pS, and show 50Mb SRAMs operational at 0.65V.

Source/drain extension scaling for 0.1 /spl mu/m and below channel length MOSFETs

In this paper, we investigate the scaling of source/drain extension (SDE) depth and SDE to gate overlap for 0.1 /spl mu/m and below MOSFETs. We show for the first time that a minimum SDE to gate overlap of 15-20 nm is needed to prevent drive current (I/sub DSAT/) degradation. We also show for the first time that scaling SDE vertical depths below 30-40 nm results in little to no performance benefit for 0.1 /spl mu/m devices and beyond since any improvement in short channel effects due to reduced charge sharing is offset by a large increase in external resistance and poor gate coupling between the channel and extensions.

Asymmetric source/drain extension transistor structure for high performance sub-50 nm gate length CMOS devices

In this paper, we present for the first time an asymmetric source/drain extension (SDE) transistor structure which can achieve high I/sub DSAT/ at gate dimensions below 50 nm. We demonstrate that this structure alleviates the severe I/sub DSAT/ degradation reported in the literature for devices when gate to source/drain overlap dimensions are reduced to under 20 nm/side (Thomson et al, 1998). Sub-15 nm gate to source/drain overlap is mandatory for supporting gate dimensions below 50 nm (Ghani et al, 2000). Moreover, fabrication of this structure employs a standard process flow in which SDE regions are formed by ion implantation and a subsequent drive-in anneal. Fundamental principles of device operation of the asymmetric SDE transistor are presented followed by a description of the process flow and an in-depth analysis of electrical characteristics and associated trade-offs.

Linear versus saturated drive current: tradeoffs in super steep retrograde well engineering

Compared to uniform well doping profiles the use of super steep retrograde well (SSRW) doping can significantly improve short channel effects permitting operation at smaller device sizes. However, the use of a SSRW does not significantly increase saturated drive current for these devices due to reduced drain saturation voltages (V/sub DSAT/). The reduction in V/sub DSAT/ occurs because the SSRW increases the depletion bulk charge and threshold voltage near the drain at high drain biases (body effect). It is shown for the first time that unlike the saturated drive current, the linear drive current exhibits a large increase for minimum size devices resulting in significantly improved inverter switching times. Improvements in gate delay of more than 10% are reported for SSRW devices.

Scalability revisited: 100 nm PD-SOI transistors and implications for 50 nm devices

We describe 100 nm gate length PD-SOI transistors with the best SOI I/sub on/-I/sub off/ characteristics reported for the 0.18 /spl mu/m technology generation. SOI inverter delay is 7.4 ps at Vdd=1.5 V and L/sub gate/=100 nm. Inverter delays show 16% (fanout=1) and 8% Vdd(V) (fanout=4) improvement over comparable bulk CMOS. Scaling analysis for PD-SOI shows a reduced role for junction capacitance and an increased history effect for scaled devices, so that SOI has significantly diminished performance gain relative to bulk CMOS for 50 nm devices (0.1 /spl mu/m generation).