Scott McCann

Study of cracking of thin glass interposers intended for microelectronic packaging substrates

Glass interposers have gained increased attention and interest in microelectronics industry since 2010. This is because glass has a tailorable coefficient of thermal expansion (CTE), high mechanical rigidity, availability in large and thin panel form, low processing cost, smooth surface for fine line and space fabrication, and superior electrical properties. While thin glass panels offer such a plethora of benefits, there are several processing and reliability challenges that glass imposes. As a brittle material, glass has low fracture toughness and is prone to cracking. In a typical large-area glass panel processing, layers of dielectric polymers and conducting copper are sequentially deposited and patterned. Due to these temperature histories and difference in the CTE among different materials, the panel is subjected to process-induced residual stresses. When the panel is subsequently diced into smaller substrates, the glass could crack. This cracking is due to high residual stresses as well as dicing defects and possible delamination at the polymer-glass interface. This experimental and theoretical work aims to investigate thin glass cracking and understand the mechanics of such cracks, focusing on the stresses induced by build-up layers. As part of this work, glass panels of 150 x 150 mm size and 100 μm thickness were laminated on both sides with ZS-100 polymer of 10 - 22.5 μm thickness and cured. After the lamination process, 5 - 10 μm thickness of copper is then deposited through a semi-additive electroless and electrolytic plating processes. This process of polymer and copper are repeated to create a total of two metal layers on each side of the panel. The panel is then diced into 18.4 x 18.4 mm substrate coupons. Dicing defects are characterized using optical inspection. Cracking failures are documented. The unbroken substrates are thermal cycled between -40 and 125 °C. In parallel to the experimental investigation, numerical models are created based on the sequential fabrication process. Copper material properties are obtained from literature as well as from in-house nanoindentation tests. Polymer properties are obtained from vendor data, and the stress-free temperature is obtained through experiments. Dicing process is simulated by inserting a vertical crack through the panel, and various dicing defects are introduced in the singulated substrate. Energy available for crack propagation of such defects is determined through fracture mechanics approach, and design guidelines to mitigate glass fracture during dicing and reliability testing are explored.

Flip-chip on glass (FCOG) package for low warpage

As microelectronic industry moves toward stacking of dies to achieve greater performance in smaller footprint, there are several reliability concerns when assembling the stacked dies on current organic substrates. These concerns include excessive warpage, interconnect cracking, die cracking, and others. Silicon interposers are being developed to assemble the stacked dies, and then to assemble the silicon interposers onto organic substrates. Although such an approach could address stacked-die to interposer reliability concerns, there are still reliability concerns between the silicon interposer and the organic substrate. The ongoing work at the Packaging Research Center is exploring the use of glass substrates as a superior alternative to organics in I/Os and to silicon in electrical performance. In addition, glass provides intermediate and tunable coefficient of thermal expansion between silicon and organic, good mechanical rigidity, large-area panel processing for low cost, planarity, and better electrical properties. However, glass is brittle and low in thermal conductivity, and there is very little work in existing literature to examine glass as a potential substrate material. In this paper, we examine large glass panels as substrates for microelectronic packages through experiments and simulation. Starting with a 150 × 150 mm glass panel with a thickness in the range of 100 to 300 um μm, we have built alternating layers of dielectric and copper on both sides of the panel. The panels go through typical cleanroom processes such as lithography, electroplating, etc. Upon fabrication, the panels are diced into individual substrates of 25 × 25 mm, and a 10 mm × 10 mm Si die with a peripheral staggered bump pitch of 80/40 um μm is then assembled on the glass substrate by thermocompression bonding with a pre-applied no-flow underfill. The warpage of the flip-chip assembly is measured. In parallel to the experiments, numerical models have been developed. These models account for temperature-dependent properties of the dielectric as well as viscoplastic behavior of the solder. The models also mimic material addition and etching through element “birth-and-death” approach. The warpage from the models has been compared against experimental measurements for glass substrates with flip-chip assembly. It is seen that the glass substrates provide significantly lower warpage compared to organic substrates, and thus could be a potential candidate for future 3D and 2.5D systems.

Prevention of Cracking From RDL Stress and Dicing Defects in Glass Substrates

Glass substrates have outstanding electrical properties, tailorable coefficient of thermal expansion (CTE), high mechanical rigidity, availability in large and thin panel form, and smooth surface for fine line fabrication, and thus, have gained increased attention and interest in microelectronics industry since 2010. While thin glass packaging offers such a plethora of benefits, glass is a brittle material and thus is prone to failure when copper wiring and polymer layers are deposited on it. This experimental and theoretical work aims to understand the mechanics of glass cracking as a result of stress development from multilayer wiring, defect formation from panel dicing, and thermal cycling, then design a solution to prevent such cracks and demonstrate this solution. Dicing defects are simulated by adding a crack into the free edge of the glass and the energy available for crack propagation, G, is determined through a finite element based fracture mechanics approach. Moisture is well known to lower surface energy, resulting in a lower critical energy release rate for glass (GC) in the presence of moisture or water and, at the defect sizes measured, G reaches GC, indicating that the samples will crack while dicing in water. With thinner dielectric material, optimized dicing process, improved glass-polymer adhesion, and solder resist pullback, it is seen that glass cracking and glasspolymer delamination can be eliminated during dicing and subsequent thermal cycling.

Modeling, design and demonstration of low-temperature, low-pressure and high-throughput thermocompression bonding of copper interconnections without solders

High-throughput assembly technologies to form Copper (Cu) interconnections without solders at below 200°C, and pitch below 40μm has been a major challenge in the semiconductor industry. A unique solution has been demonstrated by Georgia Institute of Technology to overcome this grand challenge. This technology utilizes thermocompression bonding to form copper interconnections with process tolerances to accommodate non-coplanarities of bumps and warpage of the substrate, without solders. The bonding pressure applied for thermocompression was 365MPa, to enable Cu bump collapse by 3μm. As thermocompression bonders are generally force-limited to 400N, such high bonding pressures may hinder scalability of this technology to fine pitches with higher I/O densities. This paper addresses this manufacturability challenge with the novel Electroless Palladium Autocatalytic Gold (EPAG) surface finish instead of the standard Electroless Nickel Immersion Gold (ENIG) or Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) finish, previously used to prevent Cu oxidation for bonding load reduction down to 120MPa.

Empirical investigations on die edge defects reductions in die singulation processes for glass-panel based interposers for advanced packaging

The authors evaluated various dicing methods in order to improve the TCT reliability against SeWaRe type of failures in glass interposers fabricated by polymer lamination over thin glass sheet cores. For blade-based dicing methods, the criteria for down-selection were (i) the least glass sidewall roughness and (ii) crack-free die edge visual inspections. In this fashion, a BKM dicing blade was identified that produced SeWaRe-free interposer dies upon dicing operations. Secondly, in order to compare the fracture strengths of glass produced by blade dicing with those of known methods, bare, thin glass sheet test specimens were made. In 2-point bending fracture strengths tests, glass strengths from three different blade dicing methods are similar to other score-and-break based separation methods. Lastly, a dicing process using a R&D laser system from DISCO Corp., which is not yet released-to-market, also successfully singulated the glass interposer samples. Samples produced by both blade and laser processes have been passing the TCT accelerated reliability tests.

Process Innovations to Prevent Glass Substrate Fracture From RDL Stress and Singulation Defects

Glass is an ideal material for package substrates due to the excellent electrical properties, tailorable coefficient of thermal expansion, high mechanical rigidity, availability in large and thin panel form, and smooth surface for fine line fabrication. Glass does have challenges, arising mainly from the brittle nature of glass, and glass substrates with copper and polymer re-distribution layers can suffer brittle fracture after dicing processes. This paper demonstrates three methods to prevent cracking induced by redistribution layer (RDL) stress and dicing defect in glass substrates for RDL build-up up to 90 μm polymer and 40 μm copper. These methods are edge coating, two-step dicing, and laser ablation dicing. Edge coating is a protective layer of polymer located on the diced edge of the glass substrate. After dicing, edge coating puts the glass in compression and prevents moisture from reaching the glass and, in turn, prevents the glass cracking from RDL stresses and dicing defects. In two-step dicing, the first step is used to ablate the RDL using a laser and the second step is used for blade dicing within the ablated region to singulate the glass. The resulting structure from such a dicing process reduces stress at the free glass edge, ensuring that the glass does not crack during dicing. Two-step dicing also allows for thicker RDL build-ups while ensuring no glass cracking occurs from dicing defects. Laser ablation dicing uses a CO2 laser to singulate the glass panel into individual substrates instead of blade dicing, which reduces the dicing defect size and creates a heat affected zone. Use of laser ablation dicing allows for thicker RDL build-ups with minimal process change when compared to blade dicing.

Board-Level Reliability of 3D through Glass via Filters During Thermal Cycling

This paper theoretically and experimentally assesses the board-level reliability of glass-based 3D Integrated Passive Device (IPD) with TGV-based inductor capacitor (LC) filters in thermal cycling test. Important failure modes such as wellknown solder joint cracking and TGV failure as well as other failure modes such as glass cratering are investigated in this work. Through finite-element modeling, initial reliability predictions are made using a Morrow-Darveaux approach for solder fatigue life. To predict glass cratering, a stress-based approach is used. In the second part of this work, reliability experiments are conducted on fabricated samples, demonstrating reliable 3D IPD glass packages. Failure analysis has found that solder joint cracking and glass cratering have occurred, but no TGV failures have occurred. The experimental results are also compared to numerical predictions. Then, for future designs, the models are used to analyze the impact of key material and design parameters on the experimentally observed failure modes. It is predicted that reducing the glass core thickness will improve solder fatigue life and help prevent glass cratering. Also, TGVs are recommended to be kept away from solder joints to prevent glass cratering. Stress buffering of the dielectric also improves the reliability, though less than glass core thickness. By developing and correlating a model specifically for these devices, this work, for the first time, enables accurate study and optimization of key design parameters for 3D glass IPD radio frequency (RF) devices to achieve high mechanically reliability, high-performance long term evolution band devices, with potentially smaller footprint and thickness compared to current LTCC counterparts.

A Characterization Method for Interfacial Delamination of Copper/Epoxy Mold Compound Specimens under Mixed Mode I/III Loading

The objective of this work is to develop a combinedmode I and mode III characterization method and to use thistest method to study Copper (Cu) / Epoxy mold compound(EMC) interfacial delamination from near-mode I to nearmodeIII global loading. Using the developed test method, aseries of experiments are done with varying loading modeconditions from near-mode I to near-mode III and successfuldelamination of the Cu/EMC interface is observed in manycases. Three-dimensional finite-element analysis is carried outto get compliance vs crack length relationship for differentloading conditions and is used to determine the crack lengthindirectly. The experiments indicate that as the mode mixityincreases from mode I towards mode III, the critical loadincreases for a given crack length, and thus, the interfacialfracture energy increases with the increasing mode mixity.

Analysis of System-Level Reliability of Single-Chip Glass BGA Packages with Advanced Solders and Polymer Collars

Emerging high-performance computing systems have been aggressively driving advances in packaging technologies to meet their escalating performance and miniaturization needs. Large, high-density 2.5D silicon interposers have gained momentum with the recent split-die trend but face critical reliability challenges at board-level that are addressed by introducing an additional organic BGA package between interposer and board. Glass substrates have emerged as a promising alternative owing to the superior electrical properties, sub-5µm lithographic capability and tunable CTE of glass that enables direct SMT assembly to mother boards among other advantages. This paper investigates board-level reliability of single-chip glass BGA packages, 18.5mm × 18.5mm in body size and 100µm in thickness at 400µm BGA pitch. A parametric finite-element analysis was performed to extract the optimum glass CTE for balanced chip-and board-level reliabilities. Innovative doped solder materials and strain-relief mechanisms were evaluated to improve board-level reliability with minimum system-level impact. Daisy-chain test vehicles with low (3.3ppm/K) and high (9.8ppm/K) CTE glass substrates were fabricated and assembled at chip and board levels by Cu pillar thermocompression bonding and standard SMT reflow, respectively. Assemblies with different BGA solder alloys, SAC105, SAC305 and Indiums Mn-doped SACmTM, were subjected to thermal cycling test according to JEDEC standards. Comprehensive failure analysis was performed to evaluate fatigue life improvements with advanced interconnection materials and conclude on scalability of glass substrates for high-performance applications.

Thermocompression Bonding Process Design and Optimization for Warpage Mitigation of Ultra-Thin Low-CTE Package Assemblies

Increasing needs for functionality, performance and system miniaturization in fine-pitch consumer applications have been driving a new class of ultra-thin interposers and packages with larger body sizes, aggravating warpage. These trends gave rise to serious concerns for assembly yield and reliability, especially at board level. The recent adoption of substrate technologies with silicon-matching coefficient of thermal expansion (CTE) reinforces these concerns by introducing a large CTE mismatch between package and organic board. Warpage control and mitigation in assembly has, therefore, become critical in enabling reliable SMT interconnection of ultra-thin, large, low-CTE BGA packages to the board. Copper pillar thermocompression bonding (TCB) has emerged as a key assembly technology to improve die assembly yield at pitches below 80μm and large die sizes. In TCB, heat is applied from the die side only while the substrate is maintained at a low stage temperature, as opposed to isothermal heating in mass reflow. The temperature gradient in the package can, therefore, be finely tuned providing control over the warpage behavior. This paper investigates TCB-induced warpage and its dependence on the bonding thermal profiles in a single-chip, 200μm-thick, low-CTE organic package at 50μm pitch and 17mm x 17mm body size. Warpage trends as a function of the stage temperature were first predicted with a simple coupled thermal-structural finite-element model, then experimentally validated by Shadow-Moiré measurements of assemblies built with varying stage temperatures from 70°C to 150°C. Interactions with the thermocompression tool, in particular the effect of vacuum-coupling of the substrate to the stage, were considered and investigated. Guidelines for design of TCB profiles for warpage minimization were finally derived with considerations of assembly throughput to improve board-level SMT yield and system-level reliability.