Scott Richard Stiffler

Stress induced dislocations in silicon integrated circuits

Many of the processes used in the fabrication of silicon integrated circuits lead to the development of stress in the silicon substrate. Given enough stress, the substrate will yield by generating dislocations. We examine the formation of stress-induced dislocations in integrated circuit structures. Examples are presented from bipolar and MOS-based integrated circuit structures that were created during developmental studies. The underlying causes of oxidation-induced stress and the effect on such stress of varying oxidation conditions are discussed. The knowledge thus gained is used to explain dislocation generation during the formation of a shallow-trench isolation structure. The importance of ion-implantation processes in nucleating dislocations is illustrated using structures formed by a deep-trench isolation process and a process used to form a trench capacitor in a DRAM cell. The effect of device layout geometry on dislocation generation is also examined. We show how TEM observations can be used to provide more information than solely identifying those process conditions under which dislocations are generated. By combining TEM observations with stress analysis, we show how the sources of stress responsible for dislocation movement can be identified.

Oxidation-induced defect generation in advanced DRAM structures

Structures containing deep-trenched storage capacitors and shallow-trench isolation were examined in patterns suitable for future generation dynamic RAMs (DRAMs). These same effects were also examined in similar structures which included only the shallow isolation trenches. Observed was a strong interaction between the deep and shallow trenches, which makes structures which incorporate both types much more susceptible to oxidation-induced defect generation than those without deep trenches. It was observed that at higher oxidation temperatures, more oxide can be grown before defects are generated. This is interpreted as a combination of more-efficient visco-elastic relaxation in the oxide and a lower differential oxidation rate between the

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond

In this paper, we present a systematic performance study and modeling of on-chip deep trench (DT) decoupling capacitors for high-performance SOI microprocessors. Based on system-level simulations, it is shown that the DT decoupling capacitors (decap) offer significant area advantage over the other two conventional decoupling capacitors - Metal-oxide-semiconductor (MOS) and Metal-Insulator-Metal (MIM). The fabrication process flow of DT decap is borrowed from regular eDRAM process and adds no additional process cost to processors that utilize large eDRAM cache [1]. We demonstrate that, with new process innovations such as introduction of High-k/metal gate and new plate doping methodology, there is significant reduction in equivalent series resistance (ESR) of the trench resulting in ~3.5X improvement in half capacitance frequency for 32nm node. Further, with 22nm technology, improved ESR, DT Decaps performance is significantly enhanced, hence showing that DT-decaps can be reliably used for technology beyond 32nm.

Optimization of silicon technology for the IBM system z9

IBM 90-nm silicon-on-insulator (SOI) technology was used for the key chips in the System z9TM processor chipset. Along with system design, optimization of some critical features of this technology enabled the z9TM to achieve double the system performance of the previous generation. These technology improvements included logic and SRAM FET optimization, mask fabrication, lithography and wafer processing, and interconnect technology. Reliability improvements such as SRAM optimization and burn-in reliability screen are also described.