Steven L. Prins

Material Loss Impact on Device Performance for 32nm CMOS and Beyond

As semiconductor technology moves past the 32nm CMOS node, material loss becomes an ever more important topic. Besides impacting the size of physical features, material loss impacts electrical results, process control, and defectivity. The challenge this poses is further exacerbated by the introduction of new materials. The largest single influx of new materials has come over the last decade with the introduction of high-k/metal gate (HK/MG) materials. This paper focuses on the front-end-of-line (FEOL), summarizing key materials loss issues by process loop.

Litho/Design Co-Optimization and Area Scaling for the 22-nm Logic Node

We present a comprehensive study of area scaling for 22nm-logicnode routed metal/via layers as a function of route pitch and patterning strategy in both single-exposure (SE) and doublepatterning (DP) regimes. For each candidate route pitch (8856nm), we determine an optimal illumination scheme and develop layout rules for the metal layers. A perturbative area model is used to approximate the impact of the candidate rule set on area scaling. For the most promising SE case, we apply a novel ‘source/design optimization’ technique to further optimize illumination and rules, wherein we extend the source-mask optimization approach (1) by allowing design rules to vary in the analysis. We demonstrate that the optimal area scaling achievable with DP techniques can be vastly superior to SE, and therefore may justify the associated additional cost per wafer.

Exploring complex 2D layouts for 22nm node using double patterning/double etch approach for trench levels

With the delay of a next-node lithography solution, lithographers are required to evaluate double patterning techniques such as double pattern/double etch (DP/DE) to meet scaling targets for the 22nm logic node. The tightest design rule level to pattern has traditionally been the first metal level. For this node, target minimum pitches are below 32 nm half pitch in order to meet cell area requirements. In this paper, we explore implications of the DP/DE approach when applied to complex 2D metal patterns. In addition to evaluating stitching rules for line ends, we move into complicated patterning structures such as landing pads neighboring metal runners and arrays of dense landing pads. These feature types are critical for area scaling; however, when these structures are patterned in a DP/DE scheme, the minimum area of the features needed for each pattern layer can be quite small. In this work, we explore minimum area rules for stitching together patterns as function of overlap with first pattern, minimum area and proximity to unrelated trench features on the same pattern. These results are shown thru simulation and on the wafer scale using a DP/DE approach which uses current 28 nm node imaging techniques.