Sen-Hou Ko

Wafer edge polishing process for defect reduction during immersion lithography

The objective of this study was to examine the defect reduction effect of the wafer edge polishing step on the immersion lithography process. The experimental wafers were processed through a typical front end of line device manufacturing process and half of the wafers were processed with the wafer edge polishing just prior to the immersion lithography process. The experimental wafers were then run through two immersion lithography experiments and the defect adders on these wafers were compared and analyzed. The experimental results indicated a strong effect of the edge polishing process on reducing the particle migration from the wafer edge region to the wafer surface during the immersion lithography process.

A High Productivity and Low Topography W CMP Process Enabled by a Dual Endpoint System and Novel Pad Conditioning

The growth of the flash memory market is driving the priority for new cost reduction methods for tungsten CMP. This paper focuses on productivity enhancements that boost the wafer throughput by 82% while achieving good results for topography, rate stability, non uniformity, and defects. A dual endpoint system is described that utilizes both an eddy current sensor for real-time thickness feedback and an optical sensor to signal transition points between materials. The dual endpoint system enables an improvement in platen time balancing and contributes to better erosion results. In addition, a new approach is developed for ex situ pad conditioning that results in a further reduction in cycle time.