Senju Yamazaki

Investigation of multi-level-cell and SET operations on super-lattice phase change memories

This paper gives the optimum SET pulse with the investigation on SET current delay and the multi-level-cell (MLC) operation for super-lattice phase change memories (SL-PCMs). From the investigation, the voltage, or the electric field triggers RESET/SET transition of SL-PCM. The induced energy is also essential for changing the resistance state. In this paper, the MLC operation is also verified with RESET pulse, 1-step SET pulse and 2-step SET pulse. The measurement results indicate the 2-step SET pulse is the best for the MLC function, which realizes the precise resistance controlling. Additionally, the retention-time is measured to evaluate the reliability of MLC SL-PCM. The features of SL-PCM are not only small RESET/SET current, but also MLC operation and the SL-PCM technology provides a potential for next generation non-volatile memories.

Reliability enhancement of 1Xnm TLC for cold flash and millennium memories

Endurance and retention are measured in 1Xnm Triple Level Cell (TLC) NAND and the flexible nLC scheme (flex-nLC) is proposed to improve reliability. This method enables the use of lowest-cost TLC NAND as is, in long term storage applications such as cold flash and digital archive: millennium memory, which have 20 and 1000 years retention, respectively.

Data-retention time prediction of long-term archive SSD with flexible-nLC NAND flash

This paper proposes a new method to predict the data-retention time of long-term archive SSD with flexible-nLC NAND flash. This paper first reports that the conventional prediction overestimates the data lifetime based on the long-term data retention measurement. Then, a more precise prediction is proposed. By using this proposal, the most reliable and lowest cost memory architecture is determined. As a result, over 100-year data-retention is achieved, which is 25-times longer than the conventional TLC NAND flash memory.

Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs)

This paper proposes highly reliable coding methods for applications in two extreme conditions. n-out-of-8 level cell (nLC) is proposed for archival applications which require significantly long data-retention time with small write/erase cycle. On the other hand, for applications with large write/erase cycle and short data-retention time (enterprise application, etc.), universal asymmetric coding (UAC) is proposed. nLC reduces the number of memory states to improve the reliability with low cost overhead. In 7LC, the bit-error rate (BER) reduction will be 79% after 1k-year data retention while seven memory states are efficiently used out of eight states. By considering nLC with error-correcting codes (ECCs), the optimum number of cell levels (n) can be determined to minimize the bit-cost with given acceptable data-retention time. In UAC, the coding method is changed according to the write/erase cycle and data-retention time to keep the BER low. As a result, BER is reduced by 52% at maximum, compared with the original random pattern.

Investigation of Multi-Level-Cell Operation with 2-Step SET Pulse and SET Operation on Super-Lattice Phase Change Memories

Abstract This paper gives SET operation analysis and MLC operation for super-lattice phase change memories (SL-PCMs). In SL-PCM, the SET current is triggered by the electric field. The energy, however, is also essential for changing the resistance state. The MLC operation with 2-step SET pulse is proposed. The measurement results indicate the resistance value can be finely controlled with the 2-step SET pulse, resulting in an excellent MLC function.