Seo-Min Kim

Issues and challenges of double patterning lithography in DRAM

Double patterning lithography has been one of the candidates for sub-40nm patterning era, and has a lot of process issues to be confirmed. Last year, we presented the issues in double patterning lithography with a real flash gate pattern. Process flow was suggested and CD uniformity due to overlay was analyzed. And the layout decomposition and the two types of double patterning of positive and negative tone were studied with 1-dimensional pattern. In this paper, the implementation to DRAM patterns is examined, which consist of 2-dimensional patterns. Double patterning methods and the selection of their tone for each layer are studied, and the difficulties from the randomness of core pattern are also considered. As a result, DRAM patterns have more restrictions on the double patterning method and selection of tone, and the aggressive layout decomposition should be designed to solve the difficulty in core patterning. Therefore, 37nm DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles.

Positive and negative tone double patterning lithography for 50nm flash memory

Double patterning lithography is very fascinating way of lithography which is capable of pushing down the k1 limit below 0.25. By using double patterning lithography, we can delineate the pattern beyond resolution capability. Target pattern is decomposed into patterns within resolution capability and decomposed patterns are combined together through twice lithography and twice etch processes. Two ways, negative and positive, of doing double patterning process are contrived and studied experimentally. In this paper, various issues in double patterning lithography such as pattern decomposition, resist process on patterned topography, process window of 1/4 pitch patterning, and overlay dependent CD variation are studied on positive and negative tone double patterning respectively. Among various issues about double patterning, only the overlay controllability and productivity seemed to be dominated as visible obstacles so far.

Diffraction analysis of customized illumination technique

Various enhancement techniques such as alternating PSM, chrome-less phase lithography, double exposure, etc. have been considered as driving forces to lead the production k1 factor towards below 0.35. Among them, a layer specific optimization of illumination mode, so-called customized illumination technique receives deep attentions from lithographers recently. A new approach for illumination customization based on diffraction spectrum analysis is suggested in this paper. Illumination pupil is divided into various diffraction domains by comparing the similarity of the confined diffraction spectrum. Singular imaging property of individual diffraction domain makes it easier to build and understand the customized illumination shape. By comparing the goodness of image in each domain, it was possible to achieve the customized shape of illumination. With the help from this technique, it was found that the layout change would not gives the change in the shape of customized illumination mode.

Understanding of stochastic noise

Stochastic noise has strong impact on local variability such as LWR (Line Width Roughness), LCDU (Local Critical Dimension Uniformity) and LPE (Local Placement Error), and it is basically originated from the particle nature of photon. Statistical uncertainties of particles, same as the stochastic noises, can be analytically calculated by considering aerial image as a probability density function of photons. Contact-hole is the best pattern for counting its photon, so LCDU of contact-hole array is estimated and compared with experimental results. Among several possible statistical events from mask to resist pattern, three independent events of aerial image formation, photon absorption in resist, and chemical reaction including acid generation are considered to predict stochastic noise for both EUV (Extreme Ultra Violet) and ArF immersion lithography.

EUV mask particle adders during scanner exposure

As EUV reaches high volume manufacturing, scanner source power and reticle defectivity attract a lot of attention. Keeping a EUV mask clean after mask production is as essential as producing a clean EUV mask. Even though EUV pellicle is actively investigated, we might expose EUV masks without EUV pellicle for some time. To keep clean EUV mask under pellicle-less lithography, EUV scanner cleanliness needs to meet the requirement of high volume manufacturing. In this paper, we will show the cleanliness of EUV scanners in view of mask particle adders during scanner exposure. From this we will find several tendencies of mask particle adders depending on mask environment in scanner. Further we can categorize mask particle adders, which could show the possible causes of particle adders during exposure in scanners.

EUV mask defect analysis from mask to wafer printing

ASML NXE3100 has been introduced for EUV Pre-Production, and ASML NXE3300 for High Volume Manufacturing will be installed from this year. EUV mask defect control is the one of the concerns for introducing EUVL to device manufacturing, for current EUV mask defect level is too high to accept for device volume production. EUV mask defects come from mask blank, mask process and mask handling. To have reduced mask defect level, quality control of blank mask, optimization of EUV mask process and improvement of EUV mask handling need to be ready. In this paper, we analyze printed defects exposed from EUV full field mask at NXE3100. For this analysis we trace mask defects from mask to wafer printing. From this we will show current EUV mask’s defect type and numbers. Acceptable defect type, size and numbers for device manufacturing with EUVL will be shown. Through investigating printing result of natural ML defects, realistic level of natural ML defects will be shown.

Sub-120-nm technology compatibility of attenuated phase-shift mask in KrF and ArF lithography

This paper describes that attenuated phase shift masks (APSM) improve process margin compared to binary mask (BIM) in KrF and ArF lithography. We present the real problems to occur in the mask fabrication, process and mask error factor (MEF). As a result, sub-120nm cell patterns were delineated with 8% exposure latitude (EL) and ∼0.6 μm local depth of focus (LDOF) using 0.70NA KrF and APSM. The performance of ArF lithography (NA=0.63) shows the similar process margin with 10% EL and ∼0.6 μm LDOF. Using APSM, we could obtain 14.4% EL and ∼0.6 μm LDOF. We obtained process enhancement of 30% by using APSM. However, process instability is analyzed in a viewpoint of mask making and process issue such as mask fabrication capability, CD uniformity, and MEF. In simulation and experiment, 0.63NA ArF lithography shows resolution improvement compared to 0.70NA KrF. It is possible to obtain 100nm pattern using ArF and APSM. Also, one of common issues is to reduce the MEF, which is decided by exposure and resist process condition. MEF is increased to about 4 or more in the sub-120nm range. This effect has influence on CD uniformity and EL margin. Reducing the MEF on the wafer, we have to optimize exposure tool, process, and mask. Shorter wavelength and APSM are one of candidates to minimize MEF. Therefore, ArF APSM is looking forward to high performance lithography.

Optimization of Dipole Off-Axis Illumination by 1st-Order Efficiency Method for Sub-120 nm Node with KrF Lithography

To extend the limitation of KrF lithography into the 110 nm design rule region, dipole off-axis illumination (OAI) is suggested. We have investigated the availability of the 1st-order efficiency as a method of optimization and confirmed it in the conventional OAI. By the 1st-order-efficiency method, we have designed two dipole apertures that are capable of resolving horizontal and vertical dense patterns, and have evaluated the basic performance of the modified dipole apertures. To verify the applicability of the modified dipole apertures to memory devices, we tested a variety of patterns and obtained fine patterns with the help of optical proximity correction (OPC). In this study, we found that the optimized dipole OAI can serve as an extension method of KrF lithography for 110 nm devices.

Quantitative analysis of mask error effect on wafer CD variation in ArF lithography

This paper describes the effect of the mask errors such as mask critical dimension (CD) variation, phase and transmission error of attenuated phase shifting mask (att-PSM) on wafer CD in ArF lithography and also analyzes these errors quantitatively. Mask CD requirement using ELF and MEF is estimated firstly and mask CD should be controlled within about 7nm assuming O.7ONA ArF system with 1% illumination uniformity. Transmission error induces larger CD variation than phase error. However, phase error should be considered otherwise in that it reduces depth of focus (DOF). To control DOF degradation less than 10% in case of O.l4um and O.l6um isolated contact hole(C/H), the phase should be controlled within the range of Considering O.l4um isolated contact hole, transmission error of occupies 10% of CD tolerance. Finally, the budget of these factors are calculated in view of total wafer CD variation quantitatively except lens aberration, resist process, and etc. To reduce wafer CD variation, we should control mask CD more tightly.

EUV overlay strategy for improving MMO

EUV lithography (EUVL) is the most promising technology to extend the resolution limit, and is expected to be used if the enough source power is delivered and mask defect mitigation method is developed. However, even in that case, the number of EUV steps will be restricted by its high cost, and ArF immersion will still take a major role in the chip manufacturing. Therefore, it is important to check and improve the mix-match overlay (MMO) between EUV and ArF immersion steps. In this paper, we evaluate EUV MMO with ArF immersion system by comparing with dedicated chuck overlay (DCO). The major contributors on MMO are random and field component from overlay analysis. MMO is expected to be below 3nm by applying 18para CPETM(correction per exposure) and RegCTM(Registraion error correction). We consider High oder CPETM need to be developed for further improvement.