Seokhyeon Kim

Optimization of Envelope Tracking Power Amplifier for Base-Station Applications

We have proposed two methods of enhancing efficiency of an envelope tracking power amplifier (ET PA) from an interlock operation. The first is the utilization of sinking current. The sinking current is a critical efficiency reduction factor since it is a wasted power. To reduce the sinking current, the gate bias of the power amplifier (PA) is increased so that the sinking current is delivered to the PA and is utilized for amplification. The other one is the RF input shaping method. The input signal of ET PAs is a modulated RF signal, and the signal does not guarantee fully saturated operation of the PA at all power levels due to

Asymmetric Broadband Doherty Power Amplifier Using GaN MMIC for Femto-Cell Base-Station

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Accurate Offset Line Design of Doherty Amplifier With Compensation of Peaking Amplifier Phase Variation

nonlinearity of a device. To obtain the maximum efficiency for all of the envelope voltage, we have found the optimum RF input conditions and applied it to the input of the PA. To verify the methods, the proposed ET PA is implemented using a Cree CGH40045 GaN HEMT. For a long-term evolution 5-MHz signal with 6.5-dB peak-to-average power ratio, the PA delivers power-added efficiency of 58.76% with 40.14-dBm output power at 889 MHz.

High-Performance CMOS Power Amplifier With Improved Envelope Tracking Supply Modulator

A power amplifier (PA) for a femto-cell base station should be highly efficient and small. The efficiency for amplification of a high peak-to-average power ratio (PAPR) signal is improved by designing an asymmetric Doherty power amplifier (DPA). From the simulation result for a long-term evolution (LTE) signal with 7.2-dB PAPR, the DPA delivers the highest efficiency with 1:1.4 cell size ratio for the carrier and peaking PAs. A small size is achieved by designing the DPA using a GaN monolithic microwave integrated circuit process. For broadband operation, we employ a new circuit topology to alleviate the bandwidth limiting factors of the DPA such as a quarter-wavelength transformer, phase compensation network, and offset line. With the design concept, an asymmetric broadband DPA is implemented using a TriQuint 3MI 0.25-μm GaN-HEMT MMIC process. Across 2.1-2.7 GHz, the implemented PA deliver a drain efficiency of over 49%, a gain of over 12.6 dB, and adjacent channel leakage ratio of below -45 dBc at an average power of over 33.1 dBm for the LTE signal. This fully integrated circuit has a chip-size of 2.65 mm×1.9 mm.

Highly Linear 2-Stage Doherty Power Amplifier Using GaN MMIC

Accurate offset line design of Doherty amplifier is investigated to compensate the phase variation of the carrier and peaking amplifiers. The offset line at the peaking amplifier not only blocks the power leakage to the peaking amplifier at the OFF-state, but also assists in the load modulation like the offset line at the carrier amplifier. However, with the conventional offset line, the load is not properly modulated due to the phase variation of the class C peaking amplifier. Since the offset lines at the carrier and peaking power amplifiers (PAs) properly eliminate the reactive parts during the Doherty load modulation, the offset lines can handle the phase variation also. To compensate the phase variation, additional lines are added at the carrier and peaking amplifiers for the proper load modulation. With the new offset line, the load of the peaking amplifier can be properly modulated and the efficiency at the high power region is increased. In addition, the efficiency at the low power region is also increased due to the larger load of the carrier amplifier at the power region. The enhanced performance is validated by the Doherty PA employing CGH40045 devices at 1.94 GHz, applying drain bias voltage of 50 V. For the long term evolution signal with a 6.5 dB peak-to-average power ratio, the Doherty amplifier with the new offset line delivers a drain/power-added efficiency of 57%/54.8% which is 3.5%/3.1% higher than that with the conventional offset line at an output power of 45.4 dBm with the linearity -48.3 dBc using digital predistortion linearization.

Sequential Digital Predistortion for Two-stage Envelope Tracking Power Amplifier

A differential cascode CMOS power amplifier (PA) with a supply modulator for envelope tracking (ET) has been implemented using 0.18-μm RF CMOS technology. For maximizing the PAs performance, the CMOS power cell has been optimized. The CMOS PA employs 2nd harmonic control circuits at the input, source, and output of the PA to improve efficiency and linearity at the same time. The CMOS PA utilizes an improved ET supply modulator, which is suitable for a CMOS PA with high knee voltage. By utilizing this modulator, we achieve not only higher linearity, but also higher efficiency in all power levels. For a long-term evolution signal at 1.70 GHz with a 10-MHz bandwidth and a 16-QAM 7.5-dB peak-to-average power ratio, the CMOS ET PA module achieves a power-added efficiency of 36.6%, an error vector magnitude of 3.0%, and an adjacent channel leakage ratio of -35.6 dBc at an average output power of 28.5 dBm. The proposed ET operation reduces the total current consumption over the standalone PA, by 10% at the peak power and up to 56% at a low power.

Mitigating Phase Variation of Peaking Amplifier Using Offset Line

A power amplifier (PA) for a femto-cell base station should be highly efficient, linear and small. The efficiency for amplification of a high peak-to-average power ratio (PAPR) signal was improved by designing an asymmetric Doherty PA (DPA). The linearity was improved by applying third-order inter-modulation (IM3) cancellation method. A small size is achieved by designing the DPA using GaN MMIC process. The implemented 2-stage DPA delivers a power-added efficiency (PAE) of 38.6% and a gain of 33.4 dB with an average power of 34.2 dBm for a 7.2 dB PAPR 10 MHz bandwidth LTE signal at 2.14 GHz.

GaN HEMT MMIC Doherty Power Amplifier With High Gain and High PAE

To improve the efficiency of the main power amplifier, the envelope tracking technique is widely used. However, due to the reduced gain of the main amplifier by the envelope tracking, the driving power of the drive amplifier requires to be larger and the amplifier should be optimized accordingly for an efficiency operation. In this letter, a two stage envelope tracking power amplifier is studied for the purpose. The envelope tracking technique is applied to both the drive and main power amplifiers to improve efficiency of the drive amplifier, which is usually operated at a low efficiency. The experimental results show that the efficiency of the total system is improved by 2.1% while the efficiency of the drive amplifier is increased by 8%. In addition, to overcome a serious non-linearity due to the dual envelope tracking operation, a new sequential digital predistortion architecture is proposed and using this architecture, the linearity specification of the long term evolution signal has been successfully satisfied.

Analysis of Average Power Tracking Doherty Power Amplifier

The effect of the peaking offset line on the Doherty amplifier operation is investigated. The peaking amplifier of the Doherty structure operates at a C-bias condition for the load modulation. With the C-bias, the amplifier has a poor AM-PM characteristic due to the nonlinear input/output capacitances. The nonlinear phase variation of the peaking amplifier influences the load modulation behavior and reduces efficiency of the Doherty amplifier at a high output power region. To mitigate the nonlinear PM characteristic of the peaking amplifier, the length of the peaking offset line should be reduced from the conventional offset line. To validate the offset line design, a 2-stage Doherty amplifier is implemented at 2.655 GHz using GaN pHEMT. Due to the proper load modulation, the Doherty PA delivers a very good performance. For the LTE signal with 20 MHz bandwidth and 7.2 dB peak-to-average power ratio (PAPR), the amplifier delivers a power-added efficiency (PAE) of 49.3% and gain of 25 dB at an average output power of 49 dBm.

A highly linear dual-band Doherty power amplifier for femto-cell base stations

This paper presents an approach to maximize the gain and power-added efficiency (PAE) of a Doherty power amplifier (PA) using a 0.25 μm GaN pHEMT. The conventional carrier PA has an input matching for the ROPT load and does not deliver the 3 dB higher gain with 2ROPT load due to the mismatch and it degrades gain and PAE of the PA. To solve the problem, the input match of the carrier PA is optimized at the back-off power level with the 2ROPT output load, while the input is mismatched at a high power level. A Doherty PA with the concept is designed and implemented using a GaN pHEMT MMIC process at 1.8 GHz. The measured average output power, power-added efficiency and gain are 35.6 dBm, 56.3%, and 18.9 dB for a 10 MHz LTE signal with a 6.5 dB PAPR.