Seung-Bae Park

A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology

for 4F2 DRAM Cell Array with sub 40 nm Technology Jae-Man Yoon, Kangyoon Lee, Seung-Bae Park, Seong-Goo Kim, Hyoung-Won Seo, Young-Woong Son, Bong-Soo Kim, Hyun-Woo Chung, Choong-Ho Lee*, Won-Sok Lee* *, Dong-Chan Kim* * *, Donggun Park*, Wonshik Lee and Byung-Il Ryu ATD Team, Device Research Team*, CAEP*, PD Team***, Semiconductor R&D Division, Samsung Electronics Co., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do, 449-711, Korea Tel) 82-31-209-4741, Fax) 82-31-209-3274, E-mail)

The application of BT-FinFET technology for sub 60nm DRAM integration

In this paper, the application of body tied FinFET is presented for a technology breakthrough beyond sub 60nm. DRAM on bulk Si substrate has been successfully integrated and the characteristics were compared to recess channel and planar cell array transistor DRAM. We present a comparison of three different device structures and show damascene BT-FinFET using NWL (negative word line) scheme with low channel for a highly manufacturable DRAM for sub 60nm technology node.