Sesh Ramaswami

Process Integration Considerations for 300 mm TSV Manufacturing

Through-silicon via (TSV) will transition to high volume production when end-customer value (as exhibited by functionality, performance, form factor, etc.) are delivered at equivalent yield and cost. While this has been successfully achieved for CMOS image sensors (starting with 200 mm), significant work remains to be done in the TSV value chain (design-materials-process-packaging-test) in the communication and memory segments. This paper will address key unit process/process-integration challenges and highlight recent internal/ partner and industry findings in the context of TSV manufacturability at 300 mm.

Adhesion studies of CVD copper metallization

Abstract The adhesion of chemical vapor deposition (CVD) Cu thin films to various barriers was observed to improve with a post-deposition anneal or a physical vapor deposition (PVD) Cu flash layer on the barrier before depositing CVD Cu. The ambient exposure of the barrier before the deposition of CVD Cu has been observed to lead to degradation of adhesion in both CVD Cu seed and CVD/PVD Cu high vacuum integrated metallization schemes. The integrated CVD and PVD Cu deposition scheme exhibits better adhesion due to the inherent annealing provided during the PVD deposition which is carried out at temperatures between 300 and 400°C. We have evaluated both qualitative and quantitative tests — tape test, Stud pull test and 4-point bend test — in understanding adhesion and observed that each of these tests give different details of interface breakdown.

Robust TSV via-middle and via-reveal process integration accomplished through characterization and management of sources of variation

An overview is given of developments in unit-process and process-integration technology enabling the realization of through-silicon vias (TSVs) for 3D chip stacking. TSVs are expected to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1-3]. The fabrication sequences for forming TSVs in the middle of the line (via-middle approach) and for revealing them from the backside in the far back end of the line are described with detailed attention to major unit processes of etch, dielectric deposition, barrier and seed deposition, electrochemical deposition, and chemical-mechanical planarization. Unit-process advances are described in relation to the structural and functional requirements of the TSVs, and examples are given of co-optimization among the interdependent steps of the integrated sequence. Emphasis is given to copper vias of diameter 4 to 10μm with aspect ratio between 8 and 12. For both the viaformation and via-reveal sequence, it is shown how integration problems were overcome by a comprehensive approach.

Material, Process and Geometry Effects on Through-Silicon Via Reliability and Isolation

Through-silicon via (TSV) structures with various material and geometry configurations are assessed to study their impact on reliability, isolation and performance. Oxide liner insulators show a larger performance impact as compared to low-k liners and the effect decreases with increasing liner insulator thickness. Higher density of the TSV array causes greater stress impact on carrier mobility and increases the parasitic capacitance. Additionally, low-k liner reduces the parasitic capacitance, but exhibits lower strength and adhesion, therefore degraded reliability. These results provide an important perspective of performance and reliability trade-offs necessary for a robust TSV design.

Chemical studies of CVD Cu deposited on Ta and TaN barriers under various process conditions

Contamination in the matrix of CVD copper films and at the interface between CVD copper films and barrier layers has been characterized using XPS, SIMS, XRD and RGA. Contamination in the CVD copper matrix has been found to increase with increasing precursor flow rate and with decreasing wafer temperature. Interfacial contamination has been investigated in an attempt to quantitatively define acceptable levels of contamination and ultimately reduce the effect of these contaminants on the integrated film stack. Sputtered copper flash layers for CVD copper deposition are also shown as highly effective for reducing the levels and effects of incorporated contamination.

Correlation between aluminum alloy sputtering target metallurgical characteristics, arc initiation, and in-film defect intensity

Increasing levels of metallization, shrinking device geometries, and stringent defect density requirements have led to a continuous focus in the semiconductor manufacturing community to reduce defects generated during metal deposition by PVD techniques. Of particular interest in the metallization community is the reduction in in-film defect density in sputtered aluminum films. Pareto analysis of in-film defects in currently used interconnect metallization schemes suggest that a considerable portion of the in-film defects (up to 50%) are caused by unipolar arcing during aluminum deposition. Due to their unusual molten appearance, these defects are commonly referred to as splats. These defects can be as large as 500 micrometers , and due to their frequency of occurrence and size can significantly impact device yield in a manufacturing environment. Systematic investigations have revealed that the formation of splats, due to unipolar arcing, can be strongly correlated to the metallurgy of the aluminum alloy targets used during aluminum sputter deposition. The presence of undesirable metallurgical attributes such as alumina inclusions, porosity, oxygen content etc. are the primary causes for the occurrence of unipolar arcing. These undesirable metallurgical attributes appear to be the result of the manufacturing processes used to manufacture the aluminum alloy targets. The results of this study indicate that significant improvement in defect generation due to unipolar arcing during sputter deposition of aluminum films, and hence an improvement in device yield, is possible by reduction/elimination of the various undesirable metallurgical attributes in the aluminum alloy targets.

Influence of diffusion barriers on the nucleation and growth of CVD Cu for interconnect applications

Abstract Nucleation and growth behavior of Cu influence strongly the macroscopic properties of the resultant films. In this work the nucleation of CVD Cu on different underlayer materials is studied. It is found that nucleation on bare diffusion barrier surfaces leads to island growth and, therefore, bad wetting and adhesion. An enrichment of F, O and carbon was found at the interface between the CVD Cu film and the diffusion barrier. However CVD Cu deposited on top of Ta with a 200-A PVD Cu layer on top results in good wetting. CVD Cu films grown on a PVD Cu layer expose a highly preferred 〈111〉 orientation. In this case SIMS analysis reveals a comparably low concentration of oxygen, carbon and flourine at the interface region between the CVD Cu and the barrier. These observations shed light on relevance of surface conditions for the CVD Cu deposition process. They significantly affect both film adhesion and crystal orientation, which are crucial for the use of CVD Cu as interconnect material.

Design and manufacturing enablement for three-dimensional (3D) integrated circuits (ICs)

This paper presents an overview of design and manufacturing readiness for silicon interposer based 3D integration. We present a field programmable gate array research and development vehicle to demonstrate the capabilities of 3D technology. The characterization results show minimal performance impact due to through silicon via (TSV) to 10Gbps transceivers and potential improvement in performance by integrating metal-insulator-metal (MIM) capacitor on silicon interposer. We also provide an overview of various process steps involved in the creation and integration of TSV on silicon interposer and methods to optimize them for performance and cost. Cost reduction can be achieved by process optimization at an integrated or holistic level, better alignment of interposer specification with application requirements, and die-package co-design.

Study of wetting properties of Ti/TiN liners deposited by ion metal plasma PVD for low-temperature sub-0.25-um Al fill technology

Ti/TiN liners deposited with Vectra IMPTM (Ion Metal Plasma) PVD technology can be used as wetting layers to lower the temperature of Al planarization. The Ti/TiN liners can also be used to improve the texture and morphology of the Al overlayer. An experimental investigation was performed to study the impact of the IMP PVD process on the wetting properties of the Ti/TiN films. The Ti/TiN underlayers and the Al overlayer were studied for film morphology and texturing using AFM, XRD, and TEM techniques. It was found that the IMP Ti/TiN process can be used to control and optimize the fill capabilities of low temperature Al planarization. Parameters such as process pressure, bias, process temperature of the IMP Ti and TiN process as well as the wetting layer thickness have significant effects on the grain size, reflectivity, crystal orientation, and surface roughness of the aluminum films. Al films with high reflectivity, low roughness and hyper texturing (< 1 degree(s) FWHM) have been obtained with the integration of IMP Ti/TiN liner module with a low temperature Al planarization module. The fill capability of this integrated process exceeds that of the conventional high temperature Al planarization process at the Via level for a sub 0.25 micrometers IC process.

A holistic approach to process co-optimization for through-silicon via

As through-silicon via (TSV) technology transitions from development to production, several opportunities exist to co-optimize processes to ensure a wide process window while meeting cost targets and manufacturing robustness. Trade-offs in the via middle, via reveal, and via last integration schemes involving etch, CVD, PVD, ECD, CMP, and wafer support systems (carrier wafers) are addressed.