Seung-Jae Baik

Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory

A novel multi-level charge trap flash memory with band engineering concept on the trap layer is firstly demonstrated. The engineered band structure, Si₃N₄/Al₂O₃/Si₃N₄ (NAN) was adopted as a trap layer in place of single Si₃N₄ layer in TANOS structure (Y. Shin et al., 2005). Compared to the reference structure of single Si₃N₄ trap layer, charge trap flash memory based on NAN trap layer shows larger memory window (~10 V), which is ideal for multi-level application. In addition, highly reliable operation is obtained due to lower program/erase voltages, superior endurance, and smaller room/high temperature pre-/post-cycling charge loss (DeltaVth <0.5 V).

Characterization of threshold voltage instability after program in charge trap flash memory

We investigated threshold voltage shifts after program pulse in charge trap flash memory by measuring drain current changes. We have found threshold voltage shifts can be characterized as a function of not only the materials of tunnel oxide, trap layer, blocking layer, but also physical parameters like device size and electrical measurement environment such as program voltage target and gate bias voltage. This approach can identify the root cause of initial threshold voltage shifts in charge trap flash memory devices.

Novel transition layer engineered Si nanocrystal flash memory with MHSOS structure featuring large V/sub th/ window and fast P/E speed

In this work, we propose a MHSOS (metal gate/high-k/SRO(silicon-rich oxide)/SiO2/Si) structure showing large memory window (> 4V) with fast P/E speed (plusmn18 V, 200 mus). The erase speed is featuring faster than that of Si3 N4 and has a retention time of 10 years for 10 % charge loss. These excellent properties were obtained through the modification of the transition layer between Si-NC and SiO2 matrix in an SRO medium, as well as tunneling/blocking dielectric material optimization

Sub-6F2 Charge Trap Dynamic Random Access Memory Using a Novel Operation Scheme

For the first time, we have demonstrated the feasibility of charge trap-based devices with ultra-thin tunnel oxide for high density DRAM application. Experimental results using direct tunneling scheme show good memory characteristics such as long retention time (>1000sec), large memory window (>1V), non-destructive read, high endurance, and acceptable programming speed (~100ns). Further improvement for low operation voltage and sub-6F2 cell size can be achieved by adopting a novel hot electron injection method. This novel operation scheme is helpful for efficient programming and minimizing disturbance. Due to the simple and fully logic compatible process, charge trap DRAM is considered to be a good candidate for future high-density DRAM and SOC applications

Characterization of multi-barrier tunneling diodes and vertical transistors using 2-D device simulation

A novel memory cell which adopts a floating gate device with the writing mechanism of direct tunneling through the multiple tunnel junction(MTJ) was proposed recently. The device is known to have potential advantages of scalability, high density, high speed, long data retention time, low voltage operation, low power consumption and good endurability. Characterization and optimization of the vertical transistor with MTJ enables the construction of a novel high-density memory with high speed writing and long data retention time. This paper presents a numerical analysis of the tunnel barriers in explaining I-V characteristics of the vertical transistor. We have characterized the vertical transistor with double and triple barriers from the point of view of the central barrier. We have also performed extensive 2-D device simulation for multi barrier tunneling diodes and vertical transistors with various device parameters. Results of the present analysis are expected to provide guidelines for designing the experiments for optimal transistor fabrications.