Seung Ryong Lee

Highly Reliable and Scalable Tungsten Polymetal Gate Process for Memory Devices Using Low-Temperature Plasma Selective Gate Reoxidation

We applied a very low-temperature plasma-type selective gate reoxidation process to W/poly-Si gate for suppression of abnormal oxidation of a low contact resistive WSix/WN diffusion barrier. The device with the plasma selective gate reoxidation showed superior gate oxide reliability and improved stress immunity of transistor compared to the thermally selective gate reoxidized devices

Roles of Ti, TiN, and WN as an Interdiffusion Barrier for Tungsten Dual Polygate Stack in Memory Devices

Tungsten dual polygate (W-DPG) stacks with diffusion barriers formed by the Ti(N) process were investigated in terms of gate contact resistance (Rc) and the polydepletion effect. The Ti layer in the Ti/WN diffusion barrier is found to be converted into a TiSix/TiN bilayer during the postdeposition annealing process. The TiSix reaction between Ti and p+ polycrystalline silicon (poly-Si) effectively prevents the formation of a parasitic dielectric layer, which could lead to low-gate Rc. The TiN reaction between Ti and WN minimizes the occurrence of the TiSix reaction, which effectively reduces p+ polydepletion caused by the out-diffusion of boron during the postdeposition annealing process. Therefore, poly-Si/Ti/WN/W could be a promising tungsten dual polygate stack, which satisfies high-speed requirements in dynamic random-access memory (DRAM) devices.

Gate Oxide Reliability Characterization of Tungsten Polymetal Gate with Low-Contact-Resistive WSix/WN Diffusion Barrier in Memory Devices

Gate oxide reliability characteristics using different diffusion barrier metals for a tungsten polycrystalline silicon (poly-Si) gate stack were investigated in detail. The insertion of a thin WSix layer in a tungsten poly gate stack could effectively relieve the mechanical stress of a gate hardmask nitride film during a post thermal process, which contributes to better gate oxide reliability and the stress-immunity of the transistor. This insertion could also prevent the formation of a Si–N inter-dielectric layer, which could lower the contact resistance between poly and tungsten effectively. A W/WN/WSix/poly gate stack could be a promising candidate for a future W poly gate that shows reliable high-speed characteristics in dynamic random access memory applications.

Impact of Thin WSIX Insertion in Tungsten Polymetal Gate on Gate Oxide Reliability and Gate Contact Resistance

By inserting thin WSix layer in tungsten poly gate stack we can effectively relieve the mechanical stress of gate hard mask nitride film, which contributes to the better gate oxide reliability and stress-immunity of transistor. This insertion also could prevent the formation of Si-N dielectric layer atop poly-Si, which could lower the contact resistance between poly and tungsten effectively

Limitation of WSix/WN Diffusion Barrier for Tungsten Dual Polymetal Gate Memory Devices

We compared WSix/WN and Ti/WN diffusion barriers for tungsten dual polymetal gate (W-DPG) application, in terms of device performance and gate oxide reliability. WSix/WN diffusion barrier shows degradation of gate oxide, which is found to be due to the B-N dielectric formation and subsequent breakdown of diffusion barrier. Relatively, Ti/WN diffusion barrier shows excellent device performance in terms of R/O delay and gate oxide reliability

Influence of Hydrogen Incorporation on the Reliability of Gate Oxide Formed by Using Low-Temperature Plasma Selective Oxidation Applicable to Sub-50-nm W-Polymetal Gate Devices

This letter reveals the physical and electrical properties of silicon dioxide (Si02) formed by the plasma selective oxidation (plasma selox) using 02 and H2 gas mixture, which is applicable to sub-50-nm tungsten-polymetal gate memory devices without capping nitride film. Metal-oxide-semiconductor capacitors with gate oxide formed by the plasma selox at the process temperature in the range of 400degC-700degC showed much better time-dependent dielectric-breakdown characteristics than those formed by the conventional thermal selox at 850degC. On the other hand, in the case of very low temperature (25degC) plasma selox, the gate oxide degradation such as initial breakdown was found. It turned out to be due to the excessive hydrogen and water incorporation into the SiO2 layer through thermal desorption spectroscopy measurements.

Diffusion Barrier Characteristics of TiSix/TiN for Tungsten Dual Poly Gate in DRAM

INTRODUCTION Due to the demand of high density and high speed dynamic random access memory (DRAM), gate electrode with a low specific resistance is strongly required to reduce RC delay. For this reason, tungsten polymetal gate could be a good candidate to replace the conventional tungsten polycide gate. However, there are some controversies in choosing an adequate diffusion barrier metal which is crucial for preventing abnormal silicidation between tungsten and poly-Si during post thermal process. In interconnection process, TiN processes are well known to give good characteristics as a diffusion barrier for Al or Cu-based multilevel metallization [1]. Also TiSix/TiN bilayer was reported to show low contact resistance, low stress and flat interface. Recently, some reports have been made for the application of Ti insertion to W poly gate process with a low Rc value [2, 3]. But detailed analysis about interfacial characteristics for the TiSix/TiN diffusion barrier has not been made. Also, dual poly gate processes are strongly required to suppress the short channel effect caused by shortened gate channel length. In p-channel MOSFET, boron penetration into gate oxide could degrade device performance significantly due to flat band voltage shift and increase of interface charge trap density [4, 5]. Increasing the dielectric constant of the top surface gate oxide by plasma nitridation could block boron penetration into gate oxide effectively. However, owing to the high diffusivity of boron in tungsten, it is inevitable for boron to out-diffuse into upper W electrode during thermal processes, which results in severe poly depletion effect. Therefore, inserted barrier metal should also be act as a good barrier which prevents boron from out diffusing into W layer. In this paper, diffusion barrier characteristics of W dual poly gate which involves Ti or TiN were investigated. Barrier characteristic issues relating Ti or TiN inserted gate stack, including gate contact resistance are addressed. The effects of improving p+ poly depletion effect will be shown for W/WN/(TiN)/(Ti)/p+ poly-Si gate stack in detail.

Incorporation Effect of Thin Al2O3 Layers on ZrO2–Al2O3 Nanolaminates in a Composite Oxide–High-κ-Oxide Stack for Floating-Gate Flash Memory Devices

We demonstrate the electrical properties and reliability of ZrO2–Al2O3 nanolaminates as high-κ dielectric materials in a composite oxide–high-κ-oxide (OKO) stack for floating-gate flash memory devices with 40 nm technology nodes and beyond. The effects of incorporating thin Al2O3 layers into ZrO2 films as an inserting layer and a capping layer on the electrical properties and reliability are discussed. The incorporation of Al2O3 layers significantly improves the leakage current versus the capacitive-equivalent thickness (CET) and TDDB characteristics of the ZrO2–Al2O3 nanolaminate compared with those of the pure ZrO2 owing to the mismatch of the grain boundaries, improved resistance to silicon diffusion, and enhanced energetic-electron hardness of the high-κ film.

The incorporation effect of thin Al2O3 layers on ZrO2-Al2O3 nanolaminates in the composite oxide-high-K-oxide stack for the floating gate flash memory devices

Introduction Aggressive scaling of flash memory devices requires the inter-poly dielectrics (IPD) layer with high-K dielectric to enhance the coupling ratio [1-3]. However, most of high-K dielectrics except Al2O3 tend to be crystallized during deposition or subsequent thermal processes, forming grain boundaries which serve as leakage current paths and impurity diffusion paths [4-6]. Therefore, like HfAlO film for gate dielectric application, the incorporation of Al2O3 into high-K dielectric is needed to improve the leakage current characteristics and retard the impurity diffusion through the film [7,8]. In this paper, we fabricate ZrO2Al2O3 nanolaminates and present the effect of Al2O3 incorporation on their electrical properties and reliabilities in the composite oxide-high-K-oxide (OKO) stack.

Effect of Gate Oxide Thickness Uniformity on the Characteristics of Three-dimensional Transistors

Heung-Jae Cho, Tae-Yoon Kim, Yong Soo Kim, Se-Aug Jang, Seung Ryong Lee, Kwan-Yong Lim, Min Gyu Sung, Jong-Hyeop Kim, Sang-Won Oh, Tae-Woo Jung, Tae-Kyung Oh, Yun-Taek Hwang, Young-Hoon Kim, Hong-Seon Yang, and Jin-Woong Kim R&D Division, Hynix Semiconductor Inc., Ichon P.O. Box 1010, Ichon-si, Kyoungki-do 467-701, Korea (Phone: +82-31-630-4466, Fax: +82-31-630-4545, e-mail: heungjae.cho@hynix.com)