Navas Khan

Development of 3D silicon module with TSV for system in packaging

Portable electronic products demand multifunctional module comprising digital, RF and memory functions. Through-silicon via technology provides a means of implementing complex, multi-functional integration with a higher packing density for a System in Package. A 3D silicon module with through silicon via has been developed in this work. Thermo-mechanical analysis has been performed and through silicon via interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-stack silicon module is developed and characterized in this work. Power distribution design for the silicon carrier suitable for 5 GHz digital application is studied and characterized. The module reliability has been evaluated under temperature cycling (- 40/125degC) and drop test. Samples with over-mold and underfill passed the JEDEC drop test of 1500 G & 0.5 ms pulse duration. Thermal cycle test results showed no solder joint failure.

Development of 3-D Silicon Module With TSV for System in Packaging

Portable electronic products demand multifunctional module comprising of digital, radio frequency and memory functions. Through silicon via (TSV) technology provides a means of implementing complex, multifunctional integration with a higher packing density for a system in package. A 3-D silicon module with TSV has been developed in this paper. Thermo-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the barrier copper via is exposed by the backgrinding process. A two-stack silicon module is developed and module fabrication details are given in this paper. The module reliability has been evaluated under temperature cycling (-40/125°C ) and drop test.

Three-dimensional system-in-package using stacked silicon platform technology

In this paper, a novel method of fabricating three-dimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented. The backbone of this stacked module is the fabrication of a silicon carrier with through-hole conductive interconnects. The design, process, and assembly to fabricate silicon through-hole interconnect using a wet silicon etching method is discussed in this paper. The process optimization to fabricate silicon carriers with solder through-hole interconnect within the design tolerance has been achieved. The design and modeling methodology to optimize the package in terms of electrical aspects of the stacked module is carried out to achieve less interconnect parasitics. An integrated cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for high-power applications. Known good thin flip-chip devices with daisy chain are fabricated and attached to the silicon carrier by flip-chip processes making it a known good carrier after electrical testing. Individual known good carriers are vertically integrated to form 3-D SiP.

Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages

This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer enhancement. Besides, in the silicon carrier, there are through silicon vias (TSVs) with metal film on sidewall for electrical interconnection. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. The advantage of this 3-D stacking method is that it provides a method of simultaneously realizing electrical interconnection and fluidic path and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.

Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules

In this paper, an integrated liquid cooling system for 3-D stacked modules with high dissipation level is proposed. The fluidic interconnects in this system are elaborated and the sealing technique for different fluid interfaces is discussed. Meanwhile, the pressure drop for each part of the system is analyzed. The optimized fluidic interconnects minimizing the pressure drop have been designed and fabricated, and the compact system is integrated. In line with the fluidic interconnect design and analysis, an experimental process for hydraulic characterization of the integrated cooling system is established. The pressure drops for different fluidic interconnects in this system are measured and compared with the analyzed results.

Design and fabrication of a reliability test chip for 3D-TSV

A test chip has been designed and fabricated to validate the performance, yield and reliability of 3D chipstacks using Through Silicon Vias (TSVs). The test chip contains test structures designed to measure the electromigration performance of TSVs and microbump, thermal performance, stress in the chip as a result of thinning and die stacking, and corrosion related to moisture ingress. The structures are designed to facilitate failure analysis, allowing fault isolation to be done by electrical characterization as far as possible.

3D packaging with through ilicon via (TSV) for electrical and fluidic interconnections

In this paper a liquid cooling solution has been reported for 3-D package in PoP format. The high heat dissipating chip is mounted on a silicon carrier, which has copper through-silicon via for electrical interconnection and through-silicon hollow via for fluidic circulation. Heat enhancement structures have been embedded in the chip carrier. Cooling liquid, de-ionized water is circulated through the chip carrier and heat from the chip is extracted. The fluidic channels are isolated from electrical traces using hermetic sealing. The research work has demonstrated 100 W of heat dissipation from one stack and total of 200 W from two stacks of the package. The fluidic interconnections and sealing techniques have been discussed.

Pool boiling heat transfer enhancement by surface modification/micro-structures for electronics cooling: a review

Electronics cooling is an important aspect of the microelectronics and microsystem packaging. Liquid cooling involving boiling is emerging as main technique for high heat flux application. Primary issues related to boiling are wall temperature over shoot at boiling incipience and critical heat flux. Heat transfer enhancement has concerned the researchers and practitioners for many decades. This paper reviews experimental works done for boiling enhancement by surface modification and micro-machined structures. Boiling incipient temperature and critical heat flux by various techniques are analyzed. Aim of this review is to design a novel micro-machined structure to enhance boiling and integration of the structure with the chip for cooling 3D stacked module.

3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections

In this paper, a liquid cooling solution has been reported for 3-D package in package-on-package format. A high heat dissipating chip is mounted on a silicon carrier, which has copper through-silicon via (TSV) for electrical interconnection and hollow TSV for fluidic circulation. Heat transfer enhancement structures have been embedded in the chip carrier. Cooling liquid, de-ionized water is circulated through the chip carrier and heat from the chip is extracted. The fluidic channels are isolated from electrical traces using hermetic sealing. The research work has demonstrated liquid cooling solution for 100 W from one stack and total of 200 W from two stacks of the package. The fluidic interconnections and sealing techniques have been discussed.

Development of Single Phase Liquid Cooling Solution for 3-D Silicon Modules

Demand for increased functionalities and the trend in product miniaturization have created new challenges for electronic packaging. The move to 3-D packages combines the benefits of small footprint packages and through-silicon-vias technology to overcome the limitations. However, thermal management of such packages has become the bottleneck as cooling solutions cannot access the intermediate stacks within the package. A single phase liquid microchannel cooling solution had been designed in this paper to overcome such limitations. First, the thermal resistances within the package had been identified using a 1-D thermal network. The interconnect and silicon substrate (carrier) thermal resistances have been found to be of the same order of magnitude. Flip chip with conductive underfill is chosen as the interconnect scheme balancing the thermal, mechanical, and electrical requirements. Flow distribution in the microchannels and their impact on the thermal performance were also analyzed numerically. A dual inlet, dual outlet microchannel heatsink design with a supply plenum tapering downstream was found to provide the most even flow distribution for removing the heat away from the die. A thermal resistance of 0.15 °C/W and lower temperature variation on die can be obtained with such a microchannel array arrangement. Lower hydraulic losses arising from the shorter flow length and lower mean velocities also allowed the integrated pumps to operate either at smaller sizes or higher flowrates. The methodology to derive the cooling solution is presented with due consideration to the silicon fabrication processes involved.