Shay Reboh

New insights on strained-Si on insulator fabrication by top recrystallization of amorphized SiGe on SOI

We demonstrate the fabrication of strained Si-On-Insulator (sSOI) using a relaxation process of a compressive SiGe layer on SOI, and the transfer of lattice parameter from the relaxed SiGe to the Si layer. This process is based on a partial amorphization and recrystallization of the SiGe/Si stack. We used HRXRD (High Resolution X-Ray Diffraction) and TEM (Transmission Electron Microscopy) to characterize the microstructure of the layers. Strain and Stress evolutions throughout the process were determined using Raman spectroscopy and wafer bow measurements. Using a stack of 40 nm Si0.7Ge0.3 on 9 nm Si, we obtained tensile Si layer having a stress of + 1.6 GPa which corresponds to a 80% lattice parameter transfer from SiGe to Si.

Smart solutions for efficient dual strain integration for future FDSOI generations

We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. “STRASS” and “BOX creep” techniques (for tensily and compressively stressed channels, respectively) are for the first time integrated in a localized manner on a state-of-the-art 14nm FDSOI route. STRASS enables to achieve +1.6 GPa in SOI active regions (w.r.t. +1.3 GPa for thin BOX sSOI). BOX creep process leads to more than +10% in hole mobility and +6% in Ieff(Ioff) plots. The BOX creep efficiency is investigated with respect to device dimensions: the electrical data evolution matches the proposed mobility model based on 2D simulated stress profiles.