Shiang Yang Ong

High Performance Device Design through Parasitic Junction Capacitance Reduction and Junction Leakage Current Suppression beyond 0.1 µm Technology

High performance 0.1 µm metal oxide semiconductor field effect transistors (MOSFETs) with 70 nm physical gate length and 1.7 nm gate oxide thickness are demonstrated. By reducing the parasitic junction capacitance and suppressing the junction leakage current (Ij,leak), high-speed/low-power transistors with a superior driving current are fabricated. Careful optimization of the channel, pocket and source/drain (S/D) doping profile results in a reduction of the N+/PW area junction capacitance (Cja) to 0.8 fF/µm2 and P+/NW Cja to 0.7 fF/µm2. In addition, area diode leakage current less than 50 nA/cm2 and perimeter diode leakage current less than 0.1 fA/µm are achieved. In this work, n-type MOS (NMOS) and p-type MOS (PMOS) drive current are 625 µA/µm and 285 µA/µm, respectively, at 1.0 V with an off-state current (Ioff) of 15 nA/µm. With the reduced parasitic capacitance and the high driving current, the unloaded ring oscillator (RO) exhibits the propagation delay time of 13 ps/stage in 1.0 V operation.

Mobility and strain effects for and oriented silicon and SiGe transistor channels

The impact of compressive and tensile stress on CMOS performance is studied for <;100>; and <;110>; oriented silicon and SiGe channels. The <;110>; channel direction is found to be more stress sensitive whereas the <;100>; oriented transistor has a higher initial hole mobility. These results recommend to use the <;110>; channel orientation for high performance application due to the high drive current gain and <;100>; channel orientation for low power applications where no stress elements are included to ease the overall process complexity and to decrease costs.

Advanced gate stack work function optimization and substrate dependent strain interactions on HKMG first stacks for 28nm VLSI ultra low power technologies

Different gate stack optimizations and substrate dependent strain interactions have been studied and implemented in a cost-effective 28nm VLSI ultra low power technology. Drive current improvements for NFET I_D,SAT = 870μA/μm and PFET I_D,SAT = 465μA/μm at I_OFF = 1nA/μm and V_DS = 1V can be demonstrated by using compressive and tensile contact layers on (100)/<;110> substrates. Work function optimizations result in a proper threshold voltage adjustment and improved reliability behavior for 28nm ultra low power technologies. SOC level test design implementations show consistent yield as well as improved performance.