Shigehiko Saida

Film Properties of Low‐k Silicon Nitride Films Formed by Hexachlorodisilane and Ammonia

A low-temperature process with good step coverage of silicon nitride (SiN) formed by low-pressure chemical vapor deposition (LPCVD) has been successfully developed by using hexachlorodisilane (HCD). HCD-SiN showed a higher deposition rate than the conventional LPCVD technique performed at temperatures above 700°C. SiN films can be deposited down to 250°C using HCD. Deposition characteristics, film composition, and film properties under integrated circuit fabrication processes are measured mainly in terms of deposition temperature dependence. A low-k HCD-SiN film, formed at 450°C with a permittivity of 5.4, was applied on Cu films as an oxidation and diffusion barrier layer. The film shows excellent barrier properties and is advantageous for realizing high-performance very large scale integrated devices with Cu interconnects.

Highly reliable MONOS devices with optimized silicon nitride film having deuterium terminated charge traps

For highly reliable MONOS devices, an optimized silicon nitride film has been designed from a detailed investigation of relationships between electrically wide ranging films and device performance, and a large improvement has been realized by the powerful technique of deuterium annealing, yielding highly durable devices against endurance stress of write/erase operations.

Suppression of SiN-induced boron penetration by using SiH-free silicon nitride films formed by tetrachlorosilane and ammonia

Applications of SiH-free silicon nitride (SiN) films, formed by tetrachlorosilane (TCS) and ammonia, have been proved to effectively suppress the SiN-induced boron penetration. The SiN-induced boron penetration has been investigated in detail by using boron-doped polysilicon gated capacitors with several kinds of thick SiN films. It was clarified for the first time that the SiN-induced boron penetration becomes worse with SiH content in SiN films and deposition technique of SiH-free TCS-SiN films is essential for realization of the high-performance PMOSFETs.

Embedded trench DRAMs for sub-0.10-/spl mu/m generation by using hemispherical-grain technique and LOCOS collar process

For the future system on chip era, the embedded DRAM is one of the most important devices. Since the kinds of device increase and each device must be produced from only 10000 wafers, it is difficult to withdraw the investment cost to fabricate each device. To suppress the investment cost, the devices must be shrunk by changing the integration and the materials as little as possible. In this paper, we propose the trench capacitor scaling strategy. We show that the strategy achieves 30 fF/cell for the 0.08 /spl mu/m trench and reduces the cost of ownership (COO) and raw process time (RPT) of the 0.08 /spl mu/m trench to 80% of 0.18-/spl mu/m trench, with an investment of only

Single layer nitride capacitor dielectric film and high concentration doping technology for 1 Gb/4 Gb trench-type DRAMs

1.6 M. It is achieved by the LOCOS collar process and HSG technique.

Semiconductor integrated circuits, fabrication method for the same and semiconductor integrated circuit systems

We propose a novel CVD-SiN deposition process for Single layer Nitride film using SiCl/sub 4/ as the source material to reduce the Si-H bond in the SiN film and a high concentration doping process from vapor phase into a deep trench side-wall. Combining both technologies, an equivalent film thickness for 1 G/4 Gbit DRAM is successfully reduced below 4.0 nm without especial high dielectric constant materials.