Nobuhito Toyama

Generation of a doughnut-shaped beam using a spiral phase plate

To generate a doughnut-shaped beam, i.e., the first order of a Bessel beam, a spiral phase plate with 8 divided etching areas is fabricated with an etching accuracy of better than 6 nm. The etching depth of each area is designed so that the phase distribution of the laser beam passing through has a phase difference of π at a symmetric position with respect to the optical axis. Using a laser beam with a wavefront aberration of 1/10λ, the phase distribution of the beam passing through the plate is measured by a Shack Hartman wavefront sensor. It has been found that the beam has a spiral phase change of 2π along the optical axis. The focused beam has a circular doughnut pattern, as predicted by a theoretical calculation, and we succeeded to generate the ideal first-order of a Bessel beam.

Decomposition difficulty analysis for double patterning and the impact on photomask manufacturability

Double patterning technology (DPT) is one of the most practical candidate technologies for 45nm half-pitch or beyond while conventional single exposure (SE) is still dominant with hyper NA avoiding DPT difficulties such as split-conflict or overlay issue. However small target dimension with hyper NA and strong illumination causes OPC difficulty and small latitude of lithography and photomask fabricated with much tight specification are required for SE. Then there must be double patterning (DP) approach even for SE available resolution. In this paper DP for SE available resolution is evaluated on lithography performance, pattern decomposition, photomask fabrication and inspection load. DP includes pattern pitch doubled of SE, then lithography condition such as mask error enhancement factor (MEEF) is less impacted and the lower MEEF means less tight specification for photomask fabrication. By using Synopsys DPT software, there are no software-induced conflicts and stitching is treated to be less impact. And also this software detects split-conflicts such as triangle or square placement from contact spacing. For estimating photomask inspection load, programmed defect pattern and circuit pattern on binary mask are prepared. Smaller MEEF leads less impact to defect printing which is confirmed with AIMS evaluation. As an inspection result, there are few differences of defect sensitivity for only dense features and also few differences of false defect counts between SE and DP with less NA. But if higher NA used, DPs inspection sensitivity is able to be lowered Then inspection load for DP would be lighter than SE.

Pattern decomposition for double patterning from photomask viewpoint

Double Patterning Technology (DPT) has been evaluated and reported since 32nm half pitch is recognized to be required with conventional immersion ArF lithography. DPT requires pattern decomposition into two pattern sets and the decomposition becomes more complex for especially so-called logic pattern including irregular pattern placement and many-vertices polygons. The innocent decomposition often creates forced segmentation of those polygons and two different aspect of photomasks such as density or substantial line direction. Those decomposed photomasks not only produce large possibilities of different error behavior but also leave annoyance complexity untouched. It is well known that line-ends and dense twisted lines produce large MEF. Then tighter specification for photomask fabrication have been required since the resolution limit was getting below the exposure wavelength. So the decomposition that creates tight patterns into separate two photomasks has possibilities of the fabrication load lighter. In this paper, the decomposition of criteria for DPT which helps photomask fabrication with a small possibilities is evaluated and discussed. Furthermore though its getting to popular that overlay and CD uniformity of photomasks for DPT impact to completed CD with wafer exposure directly, considering other errors such as CD shift or phase error which are supposed to recover by exposure in addition to those errors are also studied.

PROGRESS OF NIL TEMPLATE MAKING

Nano-imprint lithography (NIL) has been counted as one of the lithography candidates for hp32nm node and beyond and has showed excellent resolution capability with remarkable low line edge roughness that is attracting many researchers in the industry who were searching for the finest patterning technology. Therefore, recently we have been focusing on the resolution improvement on the NIL templates with the 100keV acceleration voltage spot beam (SB) EB writer and the 50keV acceleration voltage variable shaped beam (VSB) EB writer. The 100keV SB writers have high resolution capability, but they show fatally low throughput if we need full chip writing. Usually templates for resolution pioneers needed just a small field (several hundred microns square or so), but recently requirements for full chip templates are increasing. For full chip writing, we have also started the resolution improvement with the 50keV VSB writers used in current 4X photomask manufacturing. The 50keV VSB writers could generate full chip pattern in a reasonable time though resolution limits are inferior to that with the 100keV SB writers. In this paper, we will show latest results with both the 100keV SB and the 50keV VSB EB writers. With the 100keV SB EB writer, we have achieved down to hp15nm resolution for line and space pattern, but found that to achieve further improvement, an innovation in pattern generation method or material would be inevitable. With the 50keV VSB EB writer, we have achieved down to hp22nm resolution for line and space pattern. Though NIL has excellent resolution capability, solutions for defect inspection and repair are not clearly shown yet. In this paper, we will show preliminary inspection results with an EB inspection tool. We tested an EB inspection tool by Hermes Microvision, Inc. (HMI), which was originally developed for and are currently used as a wafer inspection tool, and now have been started to seek the application for mask use, using a programmed defect template.

Lithographic performance comparison with various RET for 45-nm node with hyper NA

In order to realize 45 nm node lithography, strong resolution enhancement technology (RET) and water immersion will be needed. In this research, we discussed about various RET performance comparison for 45 nm node using 3D rigorous simulation. As a candidate, we chose binary mask (BIN), several kinds of attenuated phase-shifting mask (att-PSM) and chrome-less phase-shifting lithography mask (CPL). The printing performance was evaluated and compared for each RET options, after the optimizing illumination conditions, mask structure and optical proximity correction (OPC). The evaluation items of printing performance were CD-DOF, contrast-DOF, conventional ED-window and MEEF, etc. Its expected that effect of mask 3D topography becomes important at 45 nm node, so we argued about not only the case of ideal structures, but also the mask topography error effects. Several kinds of mask topography error were evaluated and we confirmed how these errors affect to printing performance.

Study of program defects of 22nm nanoimprint template with an advanced e-beam inspection system

Nanoimprint lithography (NIL) is a candidate of alternative, low cost of ownership lithography solution for deep nano-meter device manufacturing12. For the NIL template pattern making, we have been developing the processes with 100keV SB EB writer and 50keV VSB EB writer to achieve the fine resolution of near 20nm1-7. However, inspection of nanoimprint template posed a big challenge to inspection system due to the small geometry, 1x comparing to 4x of Optical mask and EUV mask. Previous studies of nanoimprint template inspection were performed indirectly on a stamped wafer and/or on a round quartz wafer13. Electron beam inspection (EBI) systems have been widely used in semiconductor fabs in nanometer technology nodes. Most commonly EBI applications are electrical defects, or voltage contrast (VC) defects detection and monitoring8-11. In this study, we used a mask EBI system developed by Hermes Microvision, Inc. (HMI) to directly inspect a NIL template with line/space and hole patterns half pitched from 22nm to 90nm and with program defects sized from 4nm to 92nm. Capability of inspection with 10nm pixel size has been demonstrated and capability of capturing program defects sized 12nm and smaller has been shown. This study proved the feasibility of EBI as inspection solution of nanoimprint template for 22nmHP and beyond.

Dry etch technology development for NIL template

Nano-imprint lithography (NIL) is expected as one of the candidates for 32nm node and below. We reported in PMJ2005 that we could achieve 30nm resolution for isolated spaces and 50nm resolution for dense features with tools used in commercial mask shops today, and with modification of widely used resist. We also reported that the CD had shifted non-negligibly from the resist to quartz trench, due to the not-vertical pattern profile of the resist. In this paper, we review the resolution limit with current photomask manufacturing tools and the 100keV spot beam writer, and investigate the pattern line edge roughness. We also report our improvement in quartz dry-etch, in particular the improvement in the pattern profile and the etch depth linearity. We found by using the spot beam writer, we can potentially achieve 10nm isolated space and 35nm dense features, but we need to optimize the resist process.

45-32-nm node photomask technology with water immersion lithography

As for 32-nm node (minimum half pitch 45-nm) logic device of the next generation, the leading semiconductor device makers propose the following three kinds of lithography techniques as a candidate, multi-exposure with water immersion lithography. So we will evaluate them. In previous work, we evaluated the resolution limit and printing performance through various pitches of 45-nm node (minimum half pitch 65-nm) lithography. We evaluated the alternate aperture phase shift mask(alt-PSM) of NA=0.93 (dry and immersion) and various resolution enhancement technologies (RETs) with off-axis and polarized illumination of NA=1.07(water immersion). The minimum k1 examined at previous time was 0.31 and 0.39 respectively. To achieve 32-nm node of the next generation with water immersion lithography, we must use higher NA but yet severe k1. The combination of the strong RET, polarization and multi-exposure is thought to be required. In order to resolve severe k1 (<0.3), the double patterning is thought as a promising candidate technology, though the disadvantageous points will appear such as very severe alignment accuracy and the twice process of wafer. In this report, we will discuss some RETs such as double dipole lithography(DDL), double patterning lithography(DPL) and alt-PSM that have sufficient printing performance through various pitches of 32-nm node. We evaluate the effect and the performance of the selected lithography side RETs and mask material RETs for each, using optical simulation software.

Simulation based defect printability analysis on attenuated phase-shifting masks

Simulated wafer images for Attenuated Phase Shift Mask (ATTPSM) features are performed by the Virtual Stepper System. The ATTPSM test reticles were prepared with programmed defects (hard defects and phase defects) on line/space patterns, contact hole patterns, and rectangle patterns for 150-nm design rules. Each defect area was inspected using KLA-Tencors UV-HR365 and SLF27 inspection systems. Virtual Stepper simulations are compared with Aerial Image Measurement System (AIMSTM) simulation at best focus and at multiple defocus levels. In addition, simulation accuracy from different inspection images is compared.

Controlling linewidth roughness in step and flash imprint lithography

Despite the remarkable progress made in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template (imprint mask). As a high fidelity replication process, the resolution of imprint lithography is determined by the ability to create a master template having the required dimensions. Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. Non chemically amplified resists, such as ZEP520A, are not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the final patterned substrate. Three experiments were performed documenting LWR in the template, imprint, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3σ), and independent of the processing step and feature size.