S. Sugawa

Random Telegraph Signal Statistical Analysis using a Very Large-scale Array TEG with 1M MOSFETs

In this paper, we propose an advanced Test Element Group (TEG) which can measure a large number (10 MOSFETs) of electrical characteristics or noise characteristics with high accuracy in a very short time (0.2 sec/frame). We analyzed fluctuations of these characteristics statistically using this TEG, as the result, we confirmed that frequencies of the Random Telegraph Signal (RTS) appearance and amplitudes of the RTS become larger with the scaling-down from statistical analysis. We did not find a correlation between DC characteristic fluctuations and random noise which is caused by RTS.

Statistical analysis of Random Telegraph Noise reduction effect by separating channel from the interface

Random Telegraph Noise (RTN) has become one of the most important problems in the continuous downscaling of CMOS circuitry. We demonstrate the RTN reduction by introducing buried channel (BC) MOSFETs and discusse its reduction mechanism. Because of the larger distance between channel and SiO2/Si interface, it is more difficult for conduction carriers to be captured in and emitted from the insulator. The effective coulomb blockade radius of charged traps is small since the channel is separated from the SiO2/Si interface and locates widely and apart from the Si/SiO2 interface. Hence, the impact of charged traps is small, resulting in a decrease of probability of RTN, especially RTN with large amplitude. The separation of trap-channel distance and wider channel width are the key parameters to suppress the transition probability between the trap and channel and the influence of trapped charge to the channel.

A Test Structure for Statistical Evaluation of Characteristics Variability in a Very Large Number of MOSFETs

We have proposed and developed a test structure for evaluating electrical characteristics variability of a large number of MOSFETs in very short time using very simple circuit structure. The electrical characteristics such as threshold voltage, subthreshold swings (S-factors, random telegraph signal noise, and so on, can be measured in over one million MOSFETs. This new test structure circuit and results measured by this circuit are very efficient in developing processes, process equipment and device structure which suppress variability.

The study of time constant analysis in random telegraph noise at the subthreshold voltage region

We extracted time constants capture and emission of Random Telegraph Noise (RTN), and their dependencies of the gate-source voltage from numerous MOSFETs and discuss the trapping and detrapping processes of carriers at the subthreshold voltage region. The dependence of time to capture on gate-source voltage cannot be determined by the trap depth from the interface and but by the distance between the trap and the carrier to be captured and the trap energy level. On the other hand, it is considered that the dependence of time to emission is determined by the distance between the trap and the Si/SiO2 interface and the trap energy level. It is easy to understand emission processes compared to capture processes. We observed various emission processes caused by tunneling to Si substrate side, tunneling to gate electrode side and tunneling to either Si substrate side or gate electrode side depending on gate-source voltage. Evaluating the time constants individually is indispensable to characterize the trap which causes RTN in subthreshold voltage region.

Accurate Time Constant of Random Telegraph Signal Extracted by a Sufficient Long Time Measurement in Very Large-Scale Array TEG

To suppress Random Telegraph Signal (RTS) noise in MOSFETs, it is necessary to understand the phenomena of RTS. We can extract the accurate time constant in RTS noise by measuring a huge number of MOSFETs during a long time. Time constant is useful to obtain the energy level. In this paper, we demonstrated the statistical and accurate measurement method of the time constant of RTS by a sufficient long measuring in very large-scale array TEG.

Advanced Method for Measuring Ultra-Low Contact Resistivity Between Silicide and Silicon Based on Cross Bridge Kelvin Resistor

In order to evaluate low contact resistivity precisely, we have developed a new test structure based on cross bridge Kelvin resistor. In this structure, the misalignment margin can be as small as possible. Furthermore, we had successively derived the theoretical expressions to ensure the validity of the newly developed method. This method will enable us to evaluate the silicide to silicon contact resistivity in the sub-10-8 ¿cm2 region.

Statistical evaluation for trap energy level of RTS characteristics

The energy distributions of traps which cause RTS noise using the array test pattern having a large number of n-MOS and p-MOS are investigated. The more traps which cause RTS noise located near the conduction band. The phenomena in p-MOS are almost the same as n-MOS. However, the number of traps in p-MOS is less than that in n-MOS. The tendency of the energy distribution of the traps near the conduction band edge is different from that near the valence band edge.

A UV Si-photodiode with almost 100% internal Q.E. and high transmittance on-chip multilayer dielectric stack

In this work, by optimizing the structure and thickness of the on-chip multilayer dielectric stack using SiO2 and low extinction coefficient Si3N4 with the high UV-light sensitivity photodiode technology, high external Q.E. and high stability to UV-light were both successfully obtained. By changing the structure of on-chip multilayer dielectric stack and film thickness, we obtained the photodiode with the high external Q.E. in the desired UV-light region.

Suppression of 1/f Noise in Accumulation Mode FD‐SOI MOSFETs on Si(100) and (110) Surfaces

In this paper, a new approach to reduce the 1/f noise levels in the MOSFETs on varied silicon orientations, such as Si(100) and (110) surfaces, has been carried out. We focus on the Accumulation‐mode (AM) FD‐SOI device structure and demonstrate that the 1/f noise levels in this AM FD‐SOI MOSFETs are obviously reduced on both the Si(100) and (110) surfaces.

[100] and [111] Si MOS transistors fabricated with low growth temperature (400/spl deg/C) gate oxide by Kr/O/sub 2/ microwave-excited high-density plasma

A drastic reduction in the growth temperature (400/spl deg/C) of highly reliable SiO/sub 2/ gate oxides grown by a Kr/O/sub 2/ microwave-excited high-density plasma technique is shown to yield MOS I-V characteristics comparable to those obtained in transistors with conventionally grown dry gate oxides at 900/spl deg/C. The benefits of this technique are summarized.