Shinichiro Nakagawa

Basic studies of overlay performance on immersion lithography tool

Immersion lithography with ArF light and Ultra Pure Water (UPW) is the most promising technology for semiconductor manufacturing with 65 nm hp design and below. Since Nikon completed the first full-field immersion scanner, the Engineering Evaluation Tool (EET, NA=0.85) at the end of 2004, Toshiba and Nikon have investigated overlay accuracy with the EET which uses the local fill nozzle. EET successfully demonstrated immersion tools are comparable in single machine overlay accuracy to dry tools, and immersion-dry matching has the same level overlay matching accuracy as dry-dry matching. EET also made it clear that overlay accuracy is independent of scanning speed, and both solvent-soluble topcoats, as well as developer-soluble topcoats can be used without degradation of overlay accuracy. We investigated the impact of the thermal environment on overlay accuracy also, assuming that a key technology of overlay with immersion tools must achieve thermal stabilities similar to dry tools. It was found that the temperature of supply water and loading wafer are stable enough to keep the overlay accuracy good. As for evaporation heat, water droplets on the backside of the wafer lead to overlay degradation. We have decided to equip the wafer holder of S609B, the first immersion production model, with an advanced watertight structure.

Patterning performance of hyper NA immersion lithography for 32nm node logic process

We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.

Feasibility of Ultra-Low k1 Lithography for 28nm CMOS Node

We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the 28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask topography effect and the oblique-incidence. Using the rigorous lithography simulation considering the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum pitch required in 28nm node. The optimum mask plate and illumination conditions have been decided by simulation. The experimental results for 28nm node show that the minimum pitch patterns and minimum SRAM cell are clearly resolved by single exposure.

Resist process control for 32-nm logic node and beyond with NA > 1.30 immersion exposure tool

Resist process challenges for 32-nm node and beyond are discussed in this paper. For line and space (L/S) logic patterns, we examine ways to balance the requirements of resolution-enhancement techniques (RETs). In 32-nm node logic patterning, two-dimensional (2D) layout pattern deformation becomes more severe with stronger RET (e.g., narrow angle CQUAD illumination). Also pattern collapse more frequently happens in 2D-pattern layouts when stronger RET is used. In contrast, milder RET (annular illumination) does not induce the severe pattern collapse in 2D-pattern layout. For 2D-pattern layouts, stronger RET seems to worsen image contrast and results in high background-light in the resist pattern, which induces more pattern collapse. For the minimum-pitch L/S pattern in 32-nm node logic, annular illumination is acceptable for patterning with NA1.35 scanner when high contrast resist is used. For contact/via patterns, it is necessary to expand the overlapping CD process window. Better process margin is realized through the combination of hole-shrink technique and precise acid-diffusion control in an ArF chemically amplified resist.