Shinji Mita

A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

This two-dimensional 8/spl times/8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV-resolution in a 0.3 /spl mu/m CMOS triple-well double-metal technology operates at 150 MHz from a 0.9 V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3 V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed, standby power and chip area.

Variable supply-voltage scheme for low-power high-speed CMOS digital design

This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-/spl mu/m CMOS technology which optimally controls the internal supple voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.

A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

This MPEG4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power dissipation of a conventional CMOS design. Measured power dissipation is summarized. 70% power reduction is achieved by low-power techniques at circuit and architectural levels. A 16b RISC processor provides software programmability. Binary shape decoding uses 20% of the computation power of the RISC processor at 30MHz clock, with negligible increase in chip power dissipation. Three-step hierarchical motion estimation reduces power dissipation.

A 300 MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS

A 300 MIPS/W RISC core processor with variable supply-voltage (VS) scheme in variable threshold-voltage CMOS (VTCMOS) is presented. Performance in MIPS/W can be improved by a factor of more than two with no modification in the RISC core except for substrate contacts for the VTCMOS. From a 3.3 V external power supply the VS scheme automatically generates minimum internal supply voltages which meet the demand on its operation frequency.

200 MHz video compression macrocells using low-swing differential logic

Improving the performance of fully dedicated macrocells is key to realizing HDTV-resolution video de/compression LSIs operating at more than 100 MHz, having reasonable power consumption and chip size small enough for consumer applications. Existing circuit techniques are either not sufficiently fast or are area consuming. However, these problems are overcome by using low-swing differential logic to realise such macrocells.<<ETX>>

Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codec

A variable supply-voltage (VS) scheme with a high power-conversion-efficiency DC-DC converter is presented. A new pulse width modulation (PWM) circuit for the DC-DC converter is proposed to reduce both power consumption and chip area. The power conversion efficiency reaches up to 95%, and the area is less than half of the conventional design. The VS scheme contains critical path replica circuits of an MPEG-4 codec LSI, and its output voltage is controlled by monitoring delay time of the replica circuits. Consequently the VS scheme can automatically generate minimal internal supply voltage that meets the demand from the operation frequency of an MPEG-4 codec LSI. The advantages of this circuit are successfully demonstrated through fabrication of a test chip using a 0.3 /spl mu/m CMOS technology.

Flip-flop selection technique for power-delay trade-off [video codec]

Circuit and design techniques trade off power, delay, and area of a chip by blending different types of flip-flops with different merits: F/F blending. Three types of discrete cosine transform (DCT) blocks for MPEG-4 video codec, a conventional design (Conv-DCT), a low-power design (LP-DCT), and a high-speed design (HS-DCT), are fabricated in a 0.3 /spl mu/m CMOS technology. LP-DCT consumes 24%-51% less power without speed degradation, and HS-DCT operates 25% faster than Conv-DCT.