Shinji Ohsawa

A 60 mW 10 b CMOS image sensor with column-to-column FPN reduction

A 60 mW 10b 660(H)/spl times/490(v) pixel digital CMOS image sensor with column-to-column FPN reduction introduces the double inverting amplifier with double clamp circuit for reduction of column-to-column fixed pattern noise (dark FPN and light FPN). It operates with a 3.3 V power supply and has 60 mW power consumption. This sensor is uses 0.6 /spl mu/m, triple-poly-silicon, double-metal CMOS technology.

A highly sensitive on-chip charge detector for CCD area image sensor

A novel on-chip charge detector for charge-coupled-device (CCD) image sensor applications was fabricated and evaluated. The device, called the double-gate floating surface detector, achieves a charge/voltage conversion gain of 220 mu V/electron, a noise equivalent electron of 0.5 electrons r.m.s. and a dynamic range of 79 dB over 3.58-MHz video bandwidth at room temperature. In the small-signal region under 20 electrons, which is the photon counting region for highly sensitive imaging devices, the device was evaluated by observing the discrete voltage levels corresponding to the number of signal electrons on an oscilloscope. This evaluation confirmed that the high charge voltage conversion gain is also maintained in this region. >

A 2/3-inch 2M-pixel STACK-CCD imager

Shrinking pixel size in conventional CCD imagers degrades device performance. Unsatisfactory smear noise of -90 dB is attained in a 2/3-inch 2M pixel CCD imager. The STACK-CCD imager has a great advantage regarding this problem. A 100% aperture ratio and low smear noise are maintained regardless of future pixel shrinking, because CCD scanning circuits are overlaid with an amorphous silicon (a-Si) photoconversion layer.<<ETX>>

A 2/3-in 2 million pixel STACK-CCD HDTV imager

A 2/3-in optical format 2 M pixel STACK-CCD imager has been developed. The STACK-CCD imager, overlaid with an amorphous silicon photoconversion layer, realizes a large signal charge handling capability of 1.0/spl times/10/sup 5/ electrons, a -140 dB smear noise and a 90 dB dynamic range with a newly introduced device configuration and its unique operation. The 5.0 /spl mu/m(H)/spl times/5.2 /spl mu/m(V) unit pixel imager with sufficiently low image lag has been realized by a novel bias charge injection scheme These device performances are the best ever achieved by a CCD HDTV imager. This is the first such imager satisfying the device performances required for a practical use 2/3-in 2 M pixel HDTV imager. >

Analysis of low signal level characteristics for high-sensitivity CCD charge detector

Low signal level characteristics for a highly sensitive floating surface amplifier (FSA) have been analyzed using a two-dimensional device simulator. The linearity, within 5% variance of charge/voltage conversion ratio from 0.5 to 4000 signal electrons, has been confirmed with this simulation. This result shows that it is possible to make the charge/voltage conversion ratio under 10 signal electrons linear for an actual amplifier. Furthermore, it is shown to be possible to improve the charge/voltage conversion ratio by a factor of 2 over that of the fabricated device. >

A single-layer metal-electrode CCD image sensor

A small pixel is required to reduce CCD image sensor chip size for commercial application. However, the shrinkage of pixel size adversely affects such characteristics as smear noise, sensitivity and charge-handling capability. Furthermore, a conventional overlapping double-layer polysilicon (polySi) electrode is complicated and difficult to fabricate for CCD image sensors. For process step simplicity of the transfer electrodes, aiming at low cost sensors and the smear noise reduction, a single-layer metal-electrode CCD image sensor is introduced.

Analysis of low fixed pattern noise cell structures for photoconversion layer overlaid CCD or CMOS image sensors

A new low fixed pattern noise (FPN) cell structure, which can be used for photoconversion layer overlaid CCD or CMOS image sensors, was proposed and analyzed with a two-dimensional (2-D) device simulator. One of the most serious problems for this type of image sensor is the mixing of signal charges of neighboring cells during signal charge readout. The magnitude of signal mixing was as much as 20% for the conventional 2/3-in 2-million pixel STACK-CCD cell structure. FPN was very visible as a result of this signal mixing. This time, a new cell structure was proposed and analyzed to reduce signal mixing and FPN. It was possible to reduce signal mixing to a low value of 0.7% of the signal level using the new cell structure.

A 1/3-in interline transfer CCD image sensor with a negative-feedback-type charge detector

The authors describe an interline transfer charge coupled device (CCD) area image sensor with 94-dB dynamic range and 1.0-electron RMS noise charge detector. With a new capacitance-coupled negative-feedback configuration, the saturation level of the detector is successfully extended by a factor of five, maintaining the superior low-noise characteristics. The imager with this detector has 398 (H)*492 (V) pixels in 1/3-in format image size. Moreover, 1/f noise in the output signal is successfully suppressed with a new alternate gain inversion (AGI) signal processing. >

Dark current fixed pattern noise reduction for the 2/3-in two-million pixel HDTV STACK-CCD imager

The fixed pattern noise reduction methods, surrounding channel stop structure and the hole accumulation operation, are proposed and evaluated for the 2/3-in two-million pixel STACK-CCD HDTV imager. The surrounding channel stop structure is surrounded by the channel stop region to suppress the fluctuation of the mean dark current from Si-SiO/sub 2/ interface and the depletion layer of p-n junction. The measured fixed pattern note (FPN) and signal-to-noise (S/N) ratio are improved from 45 electrons down to 19 electrons and from 49 dB up to 54 dB under the condition of F.8 and 2000 lux at 333 K, respectively. Therefore, the 2/3-in two-million pixel HDTV handy-type color camera with high S/N ratio and low FPN can be obtained.

A random noise reduction method for an amorphous silicon photoconversion layer overlaid CCD imager

A novel random noise reduction (RNR) method, which can reduce random noise generated in a storage diode (SD), has been proposed and evaluated with a cell test element. The RNR cell structure features an RNR transistor with a second storage diode, which is inserted between the SD and a vertical CCD (V-CCD). The RNR transistor controls the transfer channel potential and suppresses the random noise generated in the SD. Net first storage diode capacitance with the RNR transistor can be reduced down to (C/sub f//spl times/C/sub a/)/(C/sub f/+m/spl times/C/sub a/), where C/sub f/ is the second storage diode capacitance, C/sub a/ is the first storage diode capacitance, and m is the channel potential modulation factor. Experimentally, the RNR cell can reduce the random noise in the SD from 42 electrons [r.m.s.] down to 18 electrons [r.m.s.] for the SD capacitance of 5 fF. This makes it possible for the photoconversion layer overlaid CCD imager with the RNR cells to reproduce video images with a high S/N ratio.