Shuichi Ohya

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

A 1-Gb DRAM for file applications

A number of large capacity DRAMs have been developed recently for file applications because data storage devices play an important role in high-speed communication and graphic systems. Such file memories must have low power dissipation, high data transfer rate and low cost. A low chip-yield problem is reported to occur in the manufacture of large capacity DRAMs. To address both device requirements and yield limitations, new circuit technologies have been developed for 1 Gb DRAMs. By implementing a time-shared offset cancel sensing scheme and adopting a diagonal bit-line (DBL) cell, the chip size is reduced to 70% of that of a conventional DRAM. A defective word-line Hi-Z standby scheme and a flexible multi-macro architecture produces about twice the yield as that resulting from conventional architecture. 32 b I/Os with a pipeline circuit technique realizes a 400 MB/s data transfer rate. A 1 Gb DRAM with these features uses 0.25 /spl mu/m CMOS.

A 98 mm/sup 2/ die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell

In order to realize high-capacity and low-cost flash memory, we have developed a 64-Mb flash memory with multilevel cell operation scheme. The 64-Mb flash memory has been achieved in a 98 mm/sup 2/ die size by using four-level per cell operation scheme, NOR type cell array, and 0.4-/spl mu/m CMOS technology. Using an FN type program/erase cell allows a single 3.3 V supply voltage. In order to establish fast programming operation using Fowler-Nordheim (FN)-NOR type memory cell, we have developed a highly parallel multilevel programming technology. The drain voltage controlled multilevel programming (DCMP) scheme, the parallel multilevel verify (PMV) circuit, and the compact multilevel sense-amplifier (CMS) have been implemented to achieve 128 b parallel programming and 6.3 /spl mu/s/Byte programming speed.

A 98 mm/sup 2/ 3.3 V 64 Mb flash memory with FN-NOR type 4-level cell

A 64 Mb flash memory has a multi-level cell and 64-memory-cell parallel programming. 98 mm/sup 2/ die uses 0.4 /spl mu/m CMOS and 4-levels (2b) per cell. 3.3 V operation and 6.3 /spl mu/s/B programming are achieved by using a Fowler-Nordheim (FN) NOR memory cell. Drain-voltage controlled multilevel programming (DCMP) is the key technology for simultaneous multi-level programming in the chip. To implement DCMP, a parallel multi-level verify (PMV) circuit and the compact multi-level sense amplifier (CMS), which enable a 64-memory-cells parallel programming operation (program/program verify), are used.

Enhancement of data retention time for giga-bit DRAMs using SIMOX technology

Both N-type and P-type stacked capacitor DRAM cells (L/sub g/=0.4 /spl mu/m) were fabricated on ultra-thin SIMOX substrates, and the data retention time was compared with that of a bulk counterpart. A data retention time of 550 sec (at 25/spl deg/C) could be achieves using ultra-thin SIMOX substrates, which is 6 times longer than that of the bulk memory cell. Specifically it is demonstrated that a P-type stacked capacitor cell on an ultrathin SIMOX substrate is very attractive and promising for future giga-bit DRAM cells.<<ETX>>

A High-Speed 1-Mbit EPROM with a Ti-Silicided Gate

A high-speed and high-density 1-Mbit EPROM has been developed by utilizing a 1.0-/spl mu/m minimum design rule and Ti-silicided gate technology. Selective Ti silicidation of the poly-Si gate has been successfully employed to reduce the word line resistance. The sheet resistance has been reduced to about 2 /spl Omega///spl square/ without degrading the programming, erasing, and retention characteristics. Both Ti silicidation and device size reduction have been combined to achieve the fast access time of 100 ns.

A DSA-type Non-Volatile Memory Transistor with Self-Aligned Gates

A new structure n-channel stacked-gate type non-volatile memory transistor for both EP ROM and EEP ROM devices is presented. In this memory transistor, the P+ -region of high impurity concentration is diffusion-self-aligned (DSA) with the drain and the floating gate is.defined, also self-aligned with the control gate. Experimental results of various characteristics are presented and discussed with some analytical consideration. This memory transistor can be characterized by the ease of channel electron injection, fast ultraviolet light erasure and the electrical erasure with single positive applied voltage using surface avalanche hole injection.

Single 5V EPROM with sub-micron memory transistor and on-chip high voltage generator

A new EPROM technology has been developed that enables the device to be operated with a single 5V power supply. The key factors for the voltage reduction are: (1) The stacked gate MOS memory transistor has been scaled down to a submicron level (0.8µm channel length). (2) An on-chip high voltage generator has been provided to generate control gate voltage of 12V which requires almost no power consumption for sufficient programming. Both soft-write endurance and memory retention were estimated to be more than 10 years, showing that the single 5V EPROM technology is compatible with high density EPROM.

A new technique to minimize the EPROM cell

This paper presents a new technique to minimize the UV Erasable, Electrically Programmable, Read-Only Memory (EPROM) cell based on N-channel double polysilicon gate MOS. The new technique features a fully self-aligned floating gate structure which reduces the EPROM cell size/bit to almost that of presently most advanced mask ROMs. A new fabrication process and the experimental results for both programming and erasure are presented. The dependence of characteristics on various device parameters are discussed with emphasis on the difference from conventional devices.