Hidenobu Miyamoto

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

A 0.1-/spl mu/m delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy

A simple fabrication technology for delta-doped MOSFETs, named post-low-energy implanting selective epitaxy (PLISE) is presented. The PLISE technology needs no additional photo-lithography mask, deposition step or etching step even for CMOS devices. The only additional step is growing undoped epitaxial channel layers by UHV-CVD after the channel implantation. With this technology, delta-doped NMOSFETs with 0.1-/spl mu/m gate length were successfully fabricated. By optimizing the epi-layer thickness and the channel doping level, short-channel effects are suppressed enough to achieve 0.1-/spl mu/m gate length. Moreover, the junction capacitance at zero bias is reduced by 50%.

RuO2/TiN-based storage electrodes for (Ba, Sr)TiO3 dynamic random access memory capacitors

Sputtered (Ba, Sr)TiO 3 (BST) thin film capacitors have been fabricated with thick RuO 2 /TiN-based storage electrodes and poly-Si contact plugs, and the electrical properties of the storage electrodes have been studied. The electrode height was higher than 450 nm and the contact size was 0.8 x 0.8 μm 2 . Resistance of the storage electrodes including contact plugs can be evaluated from the dispersion observed in capacitance-frequency measurements. TiN oxidation at the RuO 2 /TiN interface and native oxide at the TiN/Si contact contribute to the electrode resistance of RuO 2 /TiN electrodes. With increasing BST deposition temperature, the thickness of oxidized TiN in RuO 2 /TiN electrbdes increases and the electrode resistance increases correspondingly. A Ru layer inserted at the RuO 2 /TiN interface, a TiN/TiSi 2 /Si junction and rapid thermal annealing in N 2 ambient of the TiN layer are effective ways to reduce the resistance of RuO 2 /TiN-based electrodes.

A 0.18 /spl mu/m CMOS hot-standby phase-locked loop using a noise-immune adaptive-gain voltage-controlled oscillator

This PLL features a hot-standby PLL (HSPLL) architecture and noise-immune circuit techniques. With this architecture, both fast lock time and low jitter are achieved by the system transfer function being changed; it is unnecessary to vary the values of system parameters in an attempt to reduce lock time. The HSPLL uses a reconfigurable delay line (RDL) that, depending upon the state of its switch circuit (SC), can operate either as a voltage-controlled delay line (VCDL) or a voltage-controlled oscillator (VCO). When the RDL is operating as a VCDL (i.e. when the total circuit is a VCDL-PLL, a first-order system), lock time is fast and jitter is low, but it is difficult to generate a frequency-multiplied signal. This makes the VCDL-PLL configuration appropriate for the unlocked state. Then, at the instant that the HSPLL changes from the unlocked state to the locked, the condition of the SC is changed to create a VCO-PLL, a second-order system in which it is easy to generate a frequency-multiplied signal but difficult to achieve fast lock time (i.e. a situation well-suited to a locked state). This HSPLL architecture allows use of the respective advantages of both VCDL- and VCO-PLLs without having to suffer from their various disadvantages. The HSPLL is implemented in 0.18 /spl mu/m CMOS and two-layer metal technology. 2010 transistors are integrated into a 480/spl times/450 /spl mu/m/sup 2/ die area. The supply voltage is 1.0 V, the power dissipation is about 2 mW, the input signal frequency is 50 MHz, and the output signal frequency is 200 MHz.

Gate Electrode Etching Using a Transformer Coupled Plasma

Gate electrode etching using a transformer coupled plasma (TCP) was studied for future device fabrication. The influence of chamber hardware configuration on plasma characteristics and etching performance has been studied for polysilicon and polycide etching. It has been found that etching and plasma uniformities greatly depend upon dielectric plate shape and position of the inductive coil on the dielectric plate, and that distance between the inductive coil and the dielectric plate has a big impact on the etching performance. This impact on the etching performance is caused by changing the capacitively coupled component in the inductively coupled plasma.

Development of a two-step electroplating process with a long-term stability for applying to Cu metallization of 0.1-/spl mu/m generation logic ULSIs

Developed a two-step copper (Cu) electroplating (EP) process using a seed-enhancement step with an alkali-metal-free Cu-pyrophosphate solution. The solution for the seed-enhancement step has low solubility of Cu compared with conventional Cu-sulfate solution and high macrothrowing power. As a result, the two-step EP solution provided a superior seed-enhancement effect and filling properties compared to conventional Cu sulfate EP. The seed-enhancement solution has excellent long-term stability of each components concentration, and there is no change of process performance over a two-month period. The authors can easily control sheet resistance (Rs) of electroplated films which correlates with thickness and nonuniformity of seed-enhancement films with no maintenance other than the addition of de-ionized (DI) water to compensate for evaporated water. The two-step EP process achieved an excellent via-chain yield and a tight distribution of electromigration (EM) lifetime compared with the conventional EP process. Thus, the two-step EP process is a promising process for manufacturing technique of 0.1-/spl mu/m generation and beyond logic LSIs.

Dry etching of bottom anti-reflective-coat and its application to gate length control

Dry etch characteristics of the organic bottom anti-reflective-coat (BARC) are studied and applied to control WSi/sub x/ polycide gate length precisely in quarter micron region, In the plasma of O/sub 2//Cl/sub 2/ gas mixture, CD (critical dimension) control of less than 0.02 /spl mu/m, as well as an infinite selective etching of BARC to WSi/sub x/ film, was established by optimizing O/sub 2/ ratio. This optimized BARC process can be applicable to 0.25 /spl mu/m level devices for increasing the pass chip yield.