Masato Sakao

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs

A novel capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) poly-Si storage node has been developed. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufacturable by optical delineation. The feasibility of the COB cell for 64-Mb DRAMs has been verified by a 64-kb test memory with 1.8- mu m/sup 2/ cells using a 0.4- mu m design rule, storage capacitance of 30 fF, 7-nm-SiO/sub 2/-equivalent dielectric film, and a storage node height of 0.5 mu m.<<ETX>>

A new DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

A new dynamic RAM (DRAM) cell structure and its fabrication technology are proposed. The proposed DRAM cell consists of a transistor on a lateral epitaxial silicon layer (TOLE) and a stacked capacitor formed in a trench. It can achieve high immunity to alpha-particle-induced noise and a low parasitic bit-line capacitance. The TOLE structure is produced by a silicon-on-insulator fabrication technology newly developed by combining epitaxial lateral overgrowth and preferential polishing. Reasonable electrical characteristics for the TOLE and high immunity against alpha-particle disturbance for the TOLE cell were confirmed. >

Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention time

This is the first detailed study of data retention characteristics of DRAM with bias ECR-CVD oxide-filled shallow trench isolation (STI). It clarifies the relationship between trench sidewall stress and data retention characteristics. Excessive stress on trench sidewalls causes strain and defect-related leakage current, and it degrades data retention time. Strain and defects are introduced by process conditions like deep trenching, high-temperature densification, and vertically etched trenching in bias ECR-CVD oxide-filled trench case. By eliminating the cause of leakage current, fully operating 0.18 /spl mu/m-rule DRAMs have been manufactured.

A new soft-error immune DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

A new DRAM cell structure, based on a new design concept, and a fabrication technology for DRAMs of 16Mbits and beyond are proposed. The proposed cell, called a transistor on a lateral epitaxial (TOLE) silicon layer cell, can achieve high immunity to alpha-particle-induced soft errors and a low parasitic bit line capacitance. The TOLE cell is produced by a silicon-on-insulator (SOI) fabrication technology newly developed by combining epitaxial lateral overgrowth(1)(ELO) and preferential polishing(2)(PP). Reasonable electrical characteristics for the TOLE transistor and excellent immunity against alpha-particle disturbance for the TOLE memory cell are confirmed.

A high-performance 0.18-/spl mu/m merged DRAM/Logic technology featuring 0.45-/spl mu/m/sup 2/ stacked capacitor cell

This paper presents a 0.18-/spl mu/m merged DRAM/Logic technology having a 0.45-/spl mu/m/sup 2/ stacked capacitor cell. A low-temperature Metal/Insulator/Silicon (MIS) capacitor process provides high storage capacitance in the small cell, as well as a fully compatible process with high-performance CMOS logic technologies. A robust Co-salicide technology eliminates additional process steps for a silicide block. A developed 4 Mbit test vehicle achieves a retention time of 16 ms at 110/spl deg/C even with a CoSi/sub 2/ layer remaining on all diffusion regions in the memory cells.

Low-temperature integrated process below 500/spl deg/C for thin Ta/sub 2/O/sub 5/ capacitor for giga-bit DRAMs

A new low-temperature integrated (LTI) process has been developed for giga-bit DRAMs with a thin Ta/sub 2/O/sub 5/ capacitor. The maximum process temperature after capacitor formation is restricted to lower than 500/spl deg/C in the LTI process. This process can reduce the capacitor leakage current by approximately four orders of magnitude in comparison with conventional high-temperature processes. A ten times improvement in data-retention time has been verified in an experimental DRAM device with 2.5 nm Ta/sub 2/O/sub 5/ capacitors by the LTI process.<<ETX>>

A CMOS/partial-SOI structure for future ULSIs

An MOS transistor formed partly on lateral epitaxial silicon film on insulator (called the TOLE structure) has been proposed and applied to a DRAM cell. The authors have investigated the potential of the CMOS-TOLE structure for application to future ultra-large-scale integrated circuits (ULSIs). The test CMOS-TOLEs had a 400-nm-thick SiO/sub 2/ film for the SOI insulator, a 100 approximately 200-nm-thick silicon film, and a 20-nm-thick gate oxide. The designed channel width and length for the CMOS-TOLEs measured were 20/2 approximately 2.5 and 6/2 mu m. The bulk part length was 1.2 mu m. The advantages and properties of the structure are discussed. It has been estimated that the necessary storage charge for the CMOS-TOLE DRAM is about 40% of that for the bulk CMOS DRAM and that the typical logic gate delay for the CMOS-TOLE is about 60% of that for the bulk CMOS. Parasitic sidewall channel formation, which is a problem for the n-channel TOLE due to its isolation structure, has been suppressed by channel side impurity control. The leakage current level has been reduced to a value approximately ten times larger than that for the conventional bulk junction.<<ETX>>

A 0.13 /spl mu/m full metal embedded DRAM technology targeting on 1.2 V, 450 MHz operation

We have developed a 0.13 /spl mu/m embedded DRAM technology, which targets high-speed and low-voltage operation, with logic performance fully compatible with 0.13 /spl mu/m pure logic. Parasitics (resistance, capacitance) of the DRAM macro limit its performances due to RC delay and IR drop. The parasitics of the new DRAM have been successfully minimized by employing the Full Metal embedded DRAM (FMD) technology which consists of a Metal-Insulator-Metal (MIM) capacitor with metal contact, and a newly developed low resistivity bitline. The results of performance simulation using a 16 Mbit DRAM macro show 1.2 V, 450 MHz of high-performance random access operation.

Ultra-high-performance 0.13-/spl mu/m embedded DRAM technology using TiN/HfO 2 /TiN/W capacitor and body-slightly-tied SOI

We present an ultra-high-performance 0.13-/spl mu/m embedded DRAM technology, which improves transistor performance in both logic devices and DRAM cells. Simulation results indicate that the typical random access cycle of a 16-Mbit DRAM core exceeds 570 MHz. The full-metal DRAM structure having a newly developed TiN/HfO/sub 2//TiN/W capacitor minimizes the aspect ratio of the cylindrical capacitor electrode to reduce contact resistance in the logic area. Integration of the embedded DRAM with BSTSOI (Body-Slightly-Tied SOI) is also demonstrated, with which the logic performance can be further improved and the DRAM cell area is free from floating-body effects.