Shuji Asai

A High Performance LDD GaAs MESFET with a Refractory Metal Gate

I . INTRODUCTION In order to achieve ultrahigh-speed pedormance in GaAs LSIs, it is quite important to make a further improvement in the load drivability of the basic togic gates and, hence, to increase the transconductance (g-) of GaAs MESFETs. To this end, many MESFET technologies have been developed demonstrating their potentialities, such as SAINTI), refractory metal gate n* self-alignment technology2), Pt buried gate layer technologyS), and closely-spaced electrode technology4).

Low-power-consumption 10-Gbps GaAs 8:1 multiplexer/1:8 demultiplexer

An ECL-compatible 10-Gbps GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) has been developed. To decrease power consumption and to maximize phase margin, the clock-generating circuit employs source-coupled FET logic (SCFL) circuits. Also, cascade-connected source-follower circuits are used in the clock buffer. These circuits can reduce the power consumption when the fan-out number is large. Direct coupled FET logic (DCFL) circuits are employed for the 2:1 MUX/1:2 DEMUX circuits operating below 5 Gbps. The ICs, which are mounted on ceramic packages, operate at up to 10 Gbps with a power consumption of 1.2 W for the MUX and 1.0 W for the DEMUX at ECL-compatible supply voltages. These power-consumption values are one-third of the previously reported values.

A GaAs buffering circuit LSI for ultra-fast data processing systems

A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 mu m. WSi-W bilayer metallization system was used to reduce the gate resistance.<<ETX>>