Masaoki Ishikawa

0.6 V suppy voltage 0.25 /spl mu/m E/D-HJFET(IS/sup 3/T) LSI technology for low power consumption and high speed LSIs

A new technology for fabricating 0.25 /spl mu/m gate E/D-heterojunction FET LSIs is developed as a step towards the development of ultralow supply voltage LSIs. This technology, which is based upon all dry-process techniques, includes the formation of a 0.25 /spl mu/m gate opening through the use of optical lithography and inner SiO/sub 2/ sidewalls. The f/sub max/ and the g/sub max/ for a Y-shaped gate E-HJFET are 108 GHz and 530 mS/mm, respectively. Excellent performances are obtained with DCFL ring oscillators using n-AlGaAs/i-InGaAs pseudomorphic E/D-HJFETs. These include 18 ps/G unloaded delay and 109 ps/G loaded delay (FI=FO=3, L=1 mm) with 0.15 mW/G at a low supply voltage of 0.6 V, where inverters have a sufficient noise margin of more than 180 mV. Also, 10 Gbps error-free operation of a selector switch is demonstrated with 9.4 mW at 0.6 V.<<ETX>>

An ultra-low-power-consumption high-speed GaAs 256/258 dual-modulus prescaler IC

This paper describes a GaAs divide-by-256/258 dual-modulus static prescaler IC. The prescaler has a pulse swallow counter-type architecture and quasi-differential switch flip-flop (QD-FF) as its basic circuit architecture. For the input buffer circuit, we have developed a circuit that we call a Source coupled push-pull circuit (SCC), which can generate high-frequency complementary signals from a single phase signal at a low supply voltage. The IC operates at up to 14.5 GHz with a power consumption of 22 mW. The power consumption is 1/100 that of a previously reported prescaler.

An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FFs. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers.

A novel high-speed low-power tri-state driver flip flop (TD-FF) for ultra-low supply voltage GaAs heterojunction FET LSIs

The authors describe a new GaAs static flip flop, called TD-FF (tri-state driver flip flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value reported for D-FFs so far. The authors also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.<<ETX>>

A 27/GHz/151 mW GaAs 256/258 dual-modulus prescaler IC with 0.1 /spl mu/m double-deck-shaped (DDS) gate E/D-HJFETs

We have developed 0.1-/spl mu/m double-deck-shaped (DDS) gate enhancement-mode (E) and depletion-mode (D) heterojunction (HJ) FET technology based upon an all-dry-etching process, which enables high current-gain cut-off frequencies (f/sub T/) in both E- and D-mode FETs above 100 GHz. We also report the first 256/258 dual-modulus prescaler IC operating above 20 GHz with low power consumption. Obtained maximum input frequency for the prescaler was 27 GHz with power consumption of 151 mW at a supply voltage of 1.2 V. This power consumption is about 1/50 of the value extrapolated from ones reported for prescalers.

An 0.1-/spl mu/m voidless double-deck-shaped (DDS) gate HJFET with reduced gate-fringing-capacitance

This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-/spl mu/m heterojunction FETs (HJFETs) which have about half the external gate fringing capacitance (C/sub f//sup ext/) of conventional T-shaped gate HJFETs. By introducing a T-shaped SiO/sub 2/-opening technique based on two-step dry-etching with W-film masks, we fabricated 0.1-/spl mu/m gate-openings which were suitable for reducing the C/sub f//sup ext/ and filling gate-metals with voidless. The fine gate-openings are completely filled with refractory WSi/Ti/Pt/Au gate-metal by using WSi-collimated sputtering and electroless Au-plating, resulting in high performance 0.1-/spl mu/m DDS gate HJFETs are fabricated. The 0.1-/spl mu/m n-Al/sub 0.2/Ga/sub 0.8/As/i-In/sub 0.15/Ga/sub 0.85/As pseudomorphic DDS gate HJFETs exhibited an excellent V/sub th/ standard-deviation (/spl sigma/V/sub th/) of 39 mV because dry-etching techniques were used in all etching-processes. Also, an HJFET covered with SiO/sub 2/ passivation film had very high performance with an f/sub T/ of 120 GHz and an f/sub max/ of 165 GHz, due to the low C/sub f//sup ext/ with the DDS gate structure. In addition, a high f/sub T/ of 151 GHz and an f/sub max/ of 186 GHz were obtained without a SiO/sub 2/ passivation film. This fabrication technology shows great promise for high-speed IC applications.

Ultra low power consumption heterojunction FET 8:1 MUX/1:8 DEMUX for 2.4 Gbps optical fiber communication systems

A gallium arsenide 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4 Gbps optical communication systems have been developed. These LSIs employ a tree-type architecture using 2:1 MUXs/1:2 DEMUXs that is suitable for high-speed and low power operation but requires precise control of clock timing. To ensure timing margins, a new timing generator and clock buffer circuit have been developed. These LSIs operate at over 2.4 Gbps with 150-mW of power consumption at a supply voltage of 0.7 V.

A 0.1-/spl mu/m double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs

This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-/spl mu/m heterojunction-FETs (HJFETs) that have half the external gate fringing capacitance (C/sub f//sup ext/) of conventional T-shaped gate HJFETs. By introducing a T-shaped SiO/sub 2/-opening technique based on two-step dry-etching with W-film masks, we have fabricated 0.1-/spl mu/m DDS gate-openings adapted to the reduction in C/sub f//sup ext/ and to the voidless-filling of gate-metals. Moreover, by using WSi-collimated sputtering and electroless Au-plating, 0.1-/spl mu/m DDS WSi/Ti/Pt/Au gate HJFETs with high uniformity and reproducibility are made. Fabricated n-Al/sub 0.2/Ga/sub 0.8/As-In/sub 0.15/Ga/sub 0.75/As HJFETs exhibit an excellent V/sub th/ standard-deviation (/spl sigma/V/sub th/) of 39 mV. Also, the HJFET covered with a SiO/sub 2/ film shows a very high millimeter-wave performance with f/sub T/ of 120 GHz and f/sub max/ of 165 GHz, due to the low C/sub f//sup ext/. In addition, a high f/sub T/ of 151 GHz and f/sub max/ of 186 GHz are obtained without a SiO/sub 2/ film.

A 150 mW 8:1 MUX and a 170 mW 1:8 DEMUX for 2.4 gb/s optical-fiber communication systems using n-AlGaAs/i-InGaAs HJFET's

An 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4-Gb/s optical communication systems have been developed using 0.35-/spl mu/m GaAs heterojunction field-effect transistors (FETs). To ensure timing margins, a new timing generator with latches and new clock buffers with cross-coupled inverters have been developed. These large-scale integrations (LSIs) operate at over 2.4 Gb/s with a power consumption of 150 mW (MUX) and 170 mW (DEMUX) at a supply voltage of 0.7 V, and at over 5 Gb/s with power consumption of 200 mW at a supply voltage of 0.8 V.

A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's

This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage, which is 1/5 of the minimum value reported for D-FFs so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.