Sadayuki Ohnishi

Hemispherical grained Si formation on in-situ phosphorus doped amorphous-Si electrode for 256 Mb DRAM's capacitor

The cylindrical capacitor structure with hemispherical grained-Si (HSG-Si) described here reliably achieves a cell capacitance of 30 fF in a 0.4 /spl mu/m-high storage electrode with a cell area of a 0.72 /spl mu/m/sup 2/ for 256 Mbit dynamic random access memory. An HSG-Si formation technology using Si/sub 2/H/sub 6/-molecule irradiation and annealing enables control of the grain density and grain size of HSG-Si fabricated selectively on the whole surface of phosphorus-doped amorphous Si cylindrical electrodes. >

A stacked capacitor technology with ECR plasma MOCVD (Ba,Sr)TiO/sub 3/ and RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gb-scale DRAMs

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO/sub 3/ thin films is described, The four-layer RuO/sub 2//Ru/TiN/TiSi/sub x/, storage node configuration allows 500/spl deg/C processing and fine-patterning down to the 0.20 /spl mu/m size by electron beam lithography and reactive ion etching. Good insulating (Ba/sub 0.4/Sr/sub 0.6/)TiO/sub 3/ (BST) films with an SiO/sub 2/ equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1/spl times/10/sup -/6 A/cm/sup 2/ at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing, A lateral step coverage of 50% for BST is observed on the 0.2 /spl mu/m size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma. Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAMs can be achieved in a capacitor area of 0.125 /spl mu/m/sup 2/ with only the 0.3 /spl mu/m high-storage electrodes.

Selective Etching of Phosphosilicate Glass with Low Pressure Vapor HF

A reliable low pressure vapor HF etch process was developed for the selective removal of phosphorus-doped silicon oxides. With this process, a high etch rate ratio of phosphosilicate glass (PSG) and borophosphosilicate glass (BPSG) over undoped oxide is obtained. The high etch selectivity is accomplished by controlling the total vapor pressure and/or the H 2 O partial pressure. Under the low vapor pressure conditions, HF/H 2 O adsorption on the oxide surface is suppressed, resulting in a low etch rate of the undoped oxide. The etching of (B)PSG is not suppressed even at low vapor pressure, since an H 3 PO 4 (H 2 O) layer is formed on the surface and fluorine species dissolve in this H 3 PO 4 (H 2 O) layer. Because of this difference in etch mechanisms, high etch rate ratios of (B)PSG to thermal oxide of over 2000 were obtained over a wide range of conditions. Further, the low pressure vapor HF etch technique was successfully applied for selective damage-free removal of the core BPSG film from cylindrical capacitor structures in DRAMs. By applying this new process, the number of process steps involved in the formation of a cylindrical capacitor can be reduced

An ECR MOCVD (Ba,Sr)TiO/sub 3/ based stacked capacitor technology with RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gbit-scale DRAMs

A high dielectric constant (Ba,Sr)TiO/sub 3/ [BST] based stacked capacitor with new RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes was developed for Gbit-scale DRAMs. Good insulating BST films with a small t/sub eq/ of 0.65 nm on the electrode sidewalls were obtained by ECR MOCVD. The four-layer storage node allows 500/spl deg/C processing and fine-patterning down to 0.20 /spl mu/m by EB lithography and RIE. A cell capacitance of 25 fF in 0.125 /spl mu/m/sup 2/ is achieved using 0.3 /spl mu/m-high storage electrodes for 1 Gbit DRAMs.

A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO/sub 3/ and RIE patterned RuO/sub 2/TiN storage nodes

A new stacked capacitor technology with high permittivity ECR MOCVD SrTiO/sub 3/ films on 1 Gbit compatible RuO/sub 2/TiN storage nodes was developed for Gigabit-scale DRAMs. A cell capacitance of 25 fF and leakage current density of 8/spl times/10/sup -7/ A/cm/sup 2/ can be achieved with this capacitor technology, using 0.5 /spl mu/m high stacked storage electrodes in a 0.125 /spl mu/m/sup 2/ capacitor area. Fine storage RuO/sub 2/TiN electrodes were patterned down to 0.2 /spl mu/m by electron beam lithography and RIE using an O/sub 2/-based etching mixture. A new low temperature ECR MOCVD technique was also developed to prepare highly reliable SrTiO/sub 3/ films to be used on the storage electrode sidewalls.<<ETX>>

1G DRAM cell with diagonal bit-line (DBL) configuration and edge operation MOS (EOS) FET

In this paper a new capacitor-over-bit line (COB) cell for 1G DRAM is proposed. The cell area of 0.375 /spl mu/m/sup 2/ was obtained with diagonal bit line (DBL) configuration. An edge operation MOS (EOS) transfer gate has been developed which provides SOI-like small S-factor and V/sub TH/-V/sub SUB/ dependence. A storage capacitance of 28.5 fF was achieved with a Ta/sub 2/O/sub 5/ dielectric film on a hemispherical grain Si (HSG) cylinder structure.<<ETX>>

Accurate Modeling Method for Cu Interconnect

This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully, incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow. We have extracted the model parameters for 0.15μm CMOS using this method and confirmed that 10%τpd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. Moreover, it is verified that the model can be applied to more advanced technologies (90nm, 65nm and 55nm CMOS). Since the interconnect delay variations due to the processes constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.