Shusuke Kawai

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication

A fully-integrated single-chip CMOS transceiver with MAC and PHY for 60GHz proximity wireless communication is presented. A 60GHz wireless communication single-chip transceiver has not yet been reported due to large power consumption issues. However, by limiting the application to high-throughput proximity transmission, thermal issues arising in a single-chip have been overcome. A 2GHz broadband OFDM single-chip transceiver suffers from SNR degradation due to the reference clock (REFCLK) and baseband clock (BBCLK) spurs in RF/analog circuits. Low frequency spurs in the clock generator (CLKPLL) due to the mixing of the ADC/DAC sampling clock (SCLK) and other clocks such as REFCLK and BBCLK have been eliminated by careful frequency planning of those clocks. In addition to that, spur suppression in digital baseband and noise-tolerant RF/analog circuit designs are employed. The spurs have been successfully suppressed to less than -35dBc. The chip achieves a PHY data-rate of 2.35Gb/s and MAC throughput of 2.0Gb/s at a distance of 4cm. Power consumption is scalable to the throughput by the introduction of fast Sleep and Awake modes. The average power consumption at a throughput of 0.2Gb/s is reduced to 36% of that at 2.0Gb/s.

A temperature variation tolerant 60 GHz Low Noise Amplifier with current compensated bias circuit

This paper presents a temperature variation tolerant 60 GHz Low Noise Amplifier (LNA) for mm-wave communication systems. The proposed temperature compensated bias circuit is utilized for the common source LNA. The temperature variation of S21 is 1.71dB in the temperature range from -20°C to 100°C, which is 47% lower than the value reported in previous work. The Figure of Merit (FoM) of the proposed LNA at 25°C is comparable to the top value of state-of-the-art work and FoM at 100°C is also comparable to those reported in the literature operated at room temperature.

A 1024-QAM capable WLAN receiver with −56.3 dB image rejection ratio using self-calibration technique

This paper presents a 1024-QAM OFDM signal capable WLAN receiver in 65 nm CMOS technology. Thermal noise-based IQ frequency-independent mismatch correction and IQ frequency-dependent mismatch correction with baseband loopback are proposed for the self-calibration in the receiver. By using proposed calibration method, neither received external signal nor RF loopback are necessary and the residual IQ mismatch of TXBB can be removed. The measured image rejection ratio of the self-calibration is −56.3 dB. The receiver achieves the extremely low EVM of −37.1 dB even with wide channel bandwidth of 80 MHz and has the ability to receive the 1024-QAM signal. The result indicates that the receiver is extendable for the 802.11ax compliant receiver that supports a higher density modulation scheme of MIMO.

A low voltage 0.8V RF receiver in 28nm CMOS for 5GHz WLAN

This paper presents a low voltage 5GHz WLAN receiver (RX) with 0.8V power supply. The RX targets 802.11ax standard implemented in CMOS technology node from 28nm to 14nm whose power supply voltage will decrease to 0.8V. The RX presents three key techniques that overcome the challenges for the low voltage operation. An RF amplifier employs a variable source degeneration to improve the linearity. A quadrature demodulator adopts a low noise biasing technique to obtain sufficiently high overdrive voltage in a passive mixer. A 3-stage feedforward operational amplifier increases the gain within 40MHz bandwidth. The RX was fabricated in 28nm CMOS process. The measurement results show the gain from −2 to 54dB, 4.3dB of NF, and −36.1dB of EVM with VHT80 256QAM when the power supply voltage is 0.8V. The presented RX achieves low voltage operation while maintaining sufficient WLAN performances.