Toshiya Mitomo

A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications

The fisrt 77 GHz frequency modulated continuos wave (FMCW) radar transceiver IC with an accurate FMCW signal generator using a 90 nm CMOS process is presented. To realize accurate FMCW radar system in CMOS, a PLL synthesizer that is able to output linear FMCW frequency is applied. Measured radar performances, output spectrum and distance of a target, show the transceiver achieves a fundamental function for radar applications.

A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS

A 60-GHz phase-locked loop (PLL) with inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80 x 40 mum2. The active area of the PLL is 0.6 x 0.6 mm2.

A 1.5GHz-modulation-range 10ms-modulation-period 180kHz rms -frequency-error 26MHz-reference mixed-mode FMCW synthesizer for mm-wave radar application

A frequency modulated continuous-wave (FMCW) radar using triangular modulation is one of the promising candidates for realizing a CMOS radar IC [1–3]. Range and velocity resolutions of the FMCW radar are determined by the bandwidth and period of triangular modulation [4]. A short-range measurement requires wide (several GHz) bandwidth, while a long-range measurement with high-velocity resolution requires moderate (hundreds of MHz) bandwidth and long (several ms) period. Furthermore, since frequency error in the FMCW signal deteriorates range and velocity accuracy, a highly linear frequency chirp signal is required. However FMCW radars reported so far [2,3] exhibit a period up to 1.5ms because a long period degrades the chirp linearity in a conventional analog PLL. In this work, an analog/digital mixed-mode 82GHz FMCW synthesizer with 1.5GHz bandwidth, a period from 1ms to 10ms and less than 180kHzrms frequency error is described. The achieved performance corresponds to range and velocity resolutions of 10cm and 1.4km/h, respectively.

A 60-GHz CMOS Receiver with Frequency Synthesizer

A 60-GHz receiver (RX) chip fabricated in 90 nm CMOS process is reported. The RX chip consists of an LNA, a downconversion mixer and a phase-locked loop synthesizer. The RX chip is capable of generating LO signal from phase-locked synthesizer. Measured power gain and NF of 22 dB and 8.4 dB were obtained at 61.5 GHz. These results indicate the possibility of realization of CMOS single-chip 60-GHz transceiver.

A 900-MHz bandwidth analog baseband circuit with 1-dB step and 30-dB gain dynamic range

A wide-bandwidth analog baseband circuit with digital gain control is implemented in a 65-nm CMOS process. The proposed circuit adopts a variable transconductance amplifier, which achieves constant bandwidth regardless of the gain settings. Bandwidth variation is less than ±1.2 % within the gain control range of 20 dB. The proposed analog baseband circuit has in-phase and quadrature-phase paths and draws 24.8 mA from a 1.2-V power supply. Measured results show that 1-dB step gain control with 0.25-dB differential nonlinearity (DNL) for 30-dB range and I/Q gain matching accuracy of 0.15 dB is achieved.

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication

A fully-integrated single-chip CMOS transceiver with MAC and PHY for 60GHz proximity wireless communication is presented. A 60GHz wireless communication single-chip transceiver has not yet been reported due to large power consumption issues. However, by limiting the application to high-throughput proximity transmission, thermal issues arising in a single-chip have been overcome. A 2GHz broadband OFDM single-chip transceiver suffers from SNR degradation due to the reference clock (REFCLK) and baseband clock (BBCLK) spurs in RF/analog circuits. Low frequency spurs in the clock generator (CLKPLL) due to the mixing of the ADC/DAC sampling clock (SCLK) and other clocks such as REFCLK and BBCLK have been eliminated by careful frequency planning of those clocks. In addition to that, spur suppression in digital baseband and noise-tolerant RF/analog circuit designs are employed. The spurs have been successfully suppressed to less than -35dBc. The chip achieves a PHY data-rate of 2.35Gb/s and MAC throughput of 2.0Gb/s at a distance of 4cm. Power consumption is scalable to the throughput by the introduction of fast Sleep and Awake modes. The average power consumption at a throughput of 0.2Gb/s is reduced to 36% of that at 2.0Gb/s.

A 60-GHz CMOS power amplifier with Marchand balun-based parallel power combiner

A novel Marchand balun-based parallel power combiner suitable for a 60-GHz CMOS power amplifier is proposed. It improves the power efficiency by solving the issues of the phase difference of the signals to be combined and the low coupling factor of the on-chip balun in scaled CMOS technologies. The power amplifier using the proposed power combiner is fabricated in a 90 nm CMOS process with 1.2 V supply. Measured power gain, output referred 1-dB compression point, and saturated output power are 11.2 dB, +8.3 dBm, and +11.2 dBm, respectively, at 60-GHz.

A temperature variation tolerant 60 GHz Low Noise Amplifier with current compensated bias circuit

This paper presents a temperature variation tolerant 60 GHz Low Noise Amplifier (LNA) for mm-wave communication systems. The proposed temperature compensated bias circuit is utilized for the common source LNA. The temperature variation of S21 is 1.71dB in the temperature range from -20°C to 100°C, which is 47% lower than the value reported in previous work. The Figure of Merit (FoM) of the proposed LNA at 25°C is comparable to the top value of state-of-the-art work and FoM at 100°C is also comparable to those reported in the literature operated at room temperature.

A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA

A direct conversion receiver for W-CDMA, which consumes extremely low power, is presented. The receiver consists of a low-noise amplifier (LNA) IC, a receiver IC and other passive components such as an RF-SAW (Surface Acoustic Wave) filter. The receiver IC includes a quadrature demodulator (QDEM) with a local oscillator (LO) divider, lowpass filters (LPFs) for channel selection, variable gain amplifiers (VGAs) with dynamic range of 80 dB, and a fractional-N synthesizer. The power consumption for the entire receiver chain was only 30.8 mA at supply voltage of 2.7 V.

A low voltage 0.8V RF receiver in 28nm CMOS for 5GHz WLAN

This paper presents a low voltage 5GHz WLAN receiver (RX) with 0.8V power supply. The RX targets 802.11ax standard implemented in CMOS technology node from 28nm to 14nm whose power supply voltage will decrease to 0.8V. The RX presents three key techniques that overcome the challenges for the low voltage operation. An RF amplifier employs a variable source degeneration to improve the linearity. A quadrature demodulator adopts a low noise biasing technique to obtain sufficiently high overdrive voltage in a passive mixer. A 3-stage feedforward operational amplifier increases the gain within 40MHz bandwidth. The RX was fabricated in 28nm CMOS process. The measurement results show the gain from −2 to 54dB, 4.3dB of NF, and −36.1dB of EVM with VHT80 256QAM when the power supply voltage is 0.8V. The presented RX achieves low voltage operation while maintaining sufficient WLAN performances.