Silvia Armini

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.

Scalability of plasma enhanced atomic layer deposited ruthenium films for interconnect applications

Ru thin films were deposited by plasma enhanced atomic layer deposition using MethylCyclopentadienylPyrrolylRuthenium (MeCpPy)Ru and N2/NH3 plasma. The growth characteristics have been studied on titanium nitride or tantalum nitride substrates of various thicknesses. On SiO2, a large incubation period has been observed, which can be resolved by the use of a metal nitride layer ofu2009∼u20090.8 nm. The growth characteristics of Ru layers deposited on ultra-thin metal nitride layers are similar to those on thick metal nitride substrates despite the fact that the metal nitride layers are not fully closed. Scaled Ru/metal nitride stacks were deposited in narrow lines down to 25 nm width. Thinning of the metal nitride does not impact the conformality of the Ru layer in the narrow lines. For the thinnest lines the Ru deposited on the side wall showed a more granular structure when compared to the bottom of the trench, which is attributed to the plasma directionality during the deposition process.

Copper Plating on Resistive Substrates, Diffusion Barrier and Alternative Seed Layers

We have studied electrochemical deposition of copper on ruthenium-tantalum (Ru-Ta) alloy, tantalum (Ta), and cobalt (Co) substrates using cyclic voltammetry and galvanostatic methods. We show that a single-step direct-plating from acidic Cu bath approach is favorable on thin Ru-Ta films, while it presents a significant challenge for plating on resistive Ta and Co substrates.

Evaluation of Metallization Options for Advanced Cu Interconnects Application

The traditional Cu interconnect barrier/seed process consisting of PVD-Ta based barrier/Cu-seed will reach its limit between 20 nm and 30 nm wide trench dimension. To extend Cu interconnect technology further, possible solutions such as PVD-RuTa, PEALD-Ru-based, CVD-Co, PVD/CVD-self-formed-MnSixOy and self-assembled monolayers (SAMs) are studied. It is shown that both PVD-RuTa and CVD-Co possess the so-called seed enhancement capability allowing Cu filling of narrow recesses. However, they exhibit limitations in terms of Cu-diffusion barrier efficiency, electromigration reliability and scalability. Despite, the concept of SAM [NH2-SAM(C3)] as Cu diffusion barrier is demonstrated, it requires maturity and compatibility within the process flow (e.g. adhesion with the Cu overlayer). Finally, it is considered that PEALD-Ru-based alloys and CVD-based MnSixOy films are serious candidates for sub-30 nm wide trench technologies because of their conformal nature and ability to act as an efficient Cu diffusion barrier in the range of 2 nm thickness.

Cobalt UBM for fine pitch microbump applications in 3DIC

In this paper we report results and challenges of replacing Cu with Co as UBM (under bump metallization) in microbumps for 3D technology applications. Cobalt has softer and single IMC (intermetallic compounds) and according to calculations using Cobalt as UBM can reduce consumption of UBM material by solder which is attractive for sub 10um pitches of microbumps. However, cobalt oxidizes very fast which results in poor wetting by solder as shown in Figure 1. This Figure shows two SEM images of cross section of 20um (left) and 50um (right) pitches microbumps from IMEC test vehicles where poor solder wetting is observed. It can be seen than in both cases Sn is deformed during TCB (thermo-compression bonding) bonding but due to oxide formation on cobalt bumps there is no reaction between Sn and Co. Such a joints may have weak electrical connection however, it is not suitable for a reliable device. Therefore surface treatment/passivation is required for cobalt bumps.

The Effect of Ar/H2 Plasma Pretreatments on Porous K=2.0 Dielectrics for Pore Sealing by Self-Assembled Monolayers Deposition

Self-assembled monolayers (SAMs) deposition is being recently explored to help sealing the pores of a k=2.0 material. In order to enable a covalent chemical low-k surface functionalization by SAMs, a hydroxyl groups density as high as 1 to 2.5 OH groups/nm2 is required. This surface modification must be carefully controlled to confine the k below 10%. In this paper, the effects of plasma temperature, time and power on the SAMs deposition and plasma-induced damage are investigated. The main findings are that there is always a trade-off between surface hydroxyl groups density and bulk damage. A thick modified layer allows the SAM molecules to penetrate inside the pores which results in a decreased porosity and an increased k value with respect to correspondent plasma-treated pristine substrates.

TSV Cu Plating and Implications for CMP

In the work presented here, we focused on fabrication of Cu nails for 3D Stacked-Integrated-Circuits (3D-SIC) applications using electrochemical deposition from the bath with model (‘open source’) additives. We have studied the effects of bath composition on the Cu fill profile and overburden, and have also examined the correlations between phenomena observed during post-plating-processing and bath composition. Based on these results, we explored different approaches to improving Cu removal rate during Chemical Mechanical Polishing (CMP).

Vapor-deposited octadecanethiol masking layer on copper to enable area selective Hf3N4 atomic layer deposition on dielectrics studied by in situ spectroscopic ellipsometry

Area-selective atomic layer deposition (AS-ALD) has attracted a great deal of attention in recent years for self-aligned accurate pattern placement with subnanometer thickness control. The authors demonstrate a methodology to achieve AS-ALD by using undecanethiol and octadecanethiol masking layers deposited selectively in vapor phase on copper versus low-κ. Their approach has been demonstrated in combination with an in situ Hf3N4 ALD. In situ spectroscopic ellipsometer was performed to investigate the blocking ability of the thiols on the copper surface against ALD nucleation. A considerable growth inhibition up to 480 cycles for Hf3N4 deposited at 170u2009°C has been observed on the copper surface, while the same functionalization did not inhibit the nucleation on the dielectric surfaces.