Zaid El-Mekki

Void-Free Filling of HAR TSVs Using a Wet Alkaline Cu Seed on CVD Co as a Replacement for PVD Cu Seed

The results of a wet alkaline seed deposition process directly on a thin adhesion promoter film, such as chemical vapor deposition (CVD) Co, are presented. This solution has been successfully used for copper plating on blanket and patterned through-silicon-via (TSVs) wafers covered with either silicon oxide/physical vapor deposition (PVD) Ta/CVD Co or silicon oxide/PVD Ti/CVD Co stacks. Such direct plated films were used as seed layers for subsequent copper plating from an in-house-made acidic Cu bath with model additives poly(ethylene glycol) (PEG), bis(3-sulfopropyl) disulfide (SPS), and Janus Green B (JGB). We report the impact of the directly plated stack composition and thicknesses on the integration of the wet alkaline seed in TSVs with 5 μm width and high aspect ratio (HAR) as high as 8:1. The conformal wet seed layer enables the achievement of a successful void-free filling using an in-house made acidic Cu bath with model additives (SPS, PEG, and JGB).

Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects

Higher performance, higher operation speed and volume shrinkage require high 3D interconnect densities. A way to meet the density specifications is to further increase the A.R. of the TSV interconnection. This requires the integration of highly conformal thin films deposition techniques in TSV flows, particularly for metallization. In this study, seed layer enhancement is applied to regular PVD Cu seed for metalizing TSV of diameter of 2μm and aspect-ratio 15:1. The results reported in this paper open a new path for process integration of high A.R. TSVs and provide a versatile and reliable building block for achieving the high density interconnects required for tomorrows 3D electronics devices.

Copper Plating on Resistive Substrates, Diffusion Barrier and Alternative Seed Layers

We have studied electrochemical deposition of copper on ruthenium-tantalum (Ru-Ta) alloy, tantalum (Ta), and cobalt (Co) substrates using cyclic voltammetry and galvanostatic methods. We show that a single-step direct-plating from acidic Cu bath approach is favorable on thin Ru-Ta films, while it presents a significant challenge for plating on resistive Ta and Co substrates.

Direct Copper Electrochemical Deposition on Ru-Based Substrates for Advanced Interconnects Target 30 nm and 1/2 Pitch Lines: From Coupon to Full-Wafer Experiments

Extending copper electrochemical deposition to 3x nm nodes and beyond requires a new plating approach that is not constrained by typical PVD copper seed step coverage performance. To this purpose, we propose a copper direct plating process on Plasma Enhanced Atomic Layer Deposition (PEALD) Ru-based resistive substrates, where the Cu seed is deposited in-situ during the front propagation from the edge to the center of the wafer. In order to understand the full-wafer copper direct plating process that occurs on these liners, the effect of plating tool advanced features, applied waveform, plating chemistry and substrate surface activation on the subsequent plated copper nucleation behavior are studied.

Through-silicon via technology for three-dimensional integrated circuit manufacturing

Higher performance, higher operation speed and volume shrinkage require high 3D TSV interconnect densities. This work focuses on a via-middle 3D process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) and before the back-end-of-line (BEOL) interconnect process. A description of the imec 300 mm TSV platform is given, and challenges towards a reliable process integration of high density high aspect-ratio 3D interconnections are also discussed in details.

TSV Cu Plating and Implications for CMP

In the work presented here, we focused on fabrication of Cu nails for 3D Stacked-Integrated-Circuits (3D-SIC) applications using electrochemical deposition from the bath with model (‘open source’) additives. We have studied the effects of bath composition on the Cu fill profile and overburden, and have also examined the correlations between phenomena observed during post-plating-processing and bath composition. Based on these results, we explored different approaches to improving Cu removal rate during Chemical Mechanical Polishing (CMP).

N5 technology node dual-damascene interconnects enabled using multi patterning

We demonstrate an integration approach to enable 16nm half-pitch interconnects suitable for the 5nm technology node using 193i Lithography, SADP, SAQP, three times Litho-Etch (LE3) and tone-inversion. A silicon-verified DOE experiment on a SAQP process suggests a tight process window for core etch and spacer depositions. We also show a novel process flow which enable us to pattern tight-pitch metal-cut (block), and effectively scale the trench CD to 12nm at pitch 32nm. Finally we discuss line resistance and resistivity obtained for the 16nm and 12nm trenches created using 193i integration flow.

Integration of a k=2.3 spin-on polymer for the sub-28nm technology node using EUV lithography

In this work we integrate an advanced k=2.3 spin-on polymer at 40nm ½ pitch. K-value restoration techniques are investigated and complete k-value restoration is demonstrated using an in-situ HeH2 plasma. An EUV compatible stack and a dielectric dual hard mask scheme is developed to pattern trenches with good uniformity and low litho-etch bias. The impact of scaling the dielectric spacing and of direct CMP on time dependent dielectric breakdown is also studied.