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A Single-Chip CMOS Bluetooth v2.1 Radio SoC

Bluetoothcopyradios are becoming pervasive in small, battery-powered devices. This is being driven by the reduced area requirements, cost, and power consumption of Bluetooth chips. As process technology scales down to 0.13 mum CMOS and beyond, the opportunities to trade off digital complexity to reduce analog requirements can enable optimized radio designs. This article presents an architecture on both the transmitter and receiver that can optimize this digital/analog trade-off while still meeting all system requirements. A polar transmitter is presented that is capable of transmitting both basic rate and enhanced data rate traffic. The low-IF receiver is also optimized, requiring very little analog filtering and using an oversampled analog- to-digital converter to move the filtering burden to the digital domain. The result is the smallest and lowest power Bluetooth radio published to date.

A single-chip CMOS bluetooth v. 2.1 radio SoC

A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced Data Rates is implemented in standard 0.13 mum CMOS technology. All functions of a Bluetooth radio are integrated in the SoC, including RF, analog and digital parts. The RF transceiver features a polar transmitter, a two-point modulated fractional-N synthesizer, a 500 kHz IF receiver with first order low-pass analog filtering, and a DeltaSigma ADC with 74 dB dynamic range. The total SoC die area is 9.2 mm2 with only 3.0 mm2 for analog and RF circuits. The basic-rate radio power consumption is below 30 mA for both receive and transmit.