Shahram Abdollahi-Alibeik

A Single-Chip CMOS Radio SoC for v2.1 Bluetooth Applications

This paper presents a Bluetooth v2.1 compliant SoC that integrates all functions of a Bluetooth radio. The transceiver comprises a two-point modulated fractional-N synthesizer, a polar transmitter, and a 500 kHz IF receiver with minimal analog filtering. The radio architecture is chosen to minimize overall die area as well as power consumption for both the basic and enhanced data rates. The SoC is implemented in a standard 0.13 mum digital CMOS technology with a die area of 9.2 mm2, of which only 3.0 mm2 is occupied by the analog and RF blocks. The basic-rate radio draws a total supply current of 29.7 mA in the receive mode and 29.4 mA in the transmit mode.

A Single-Chip CMOS Bluetooth v2.1 Radio SoC

Bluetoothcopyradios are becoming pervasive in small, battery-powered devices. This is being driven by the reduced area requirements, cost, and power consumption of Bluetooth chips. As process technology scales down to 0.13 mum CMOS and beyond, the opportunities to trade off digital complexity to reduce analog requirements can enable optimized radio designs. This article presents an architecture on both the transmitter and receiver that can optimize this digital/analog trade-off while still meeting all system requirements. A polar transmitter is presented that is capable of transmitting both basic rate and enhanced data rate traffic. The low-IF receiver is also optimized, requiring very little analog filtering and using an oversampled analog- to-digital converter to move the filtering burden to the digital domain. The result is the smallest and lowest power Bluetooth radio published to date.

Design and implementation of a CMO 802.11n SoC

Wireless local area networks based on the IEEE 802.11 standard are rapidly replacing wires within homes and offices. The latest data-rate amendment to the IEEE 802.11 standard, known as the 802.11n, provides enhanced user experience by exploiting MIMO techniques that use multiple antennas for both transmitter and receiver. In conjunction with MAC layer improvements such as aggregating data, the 802.11n standard supports PHY data rates as high as 600 Mb/s with four spatial streams. This article discusses various MAC and PHY level modifications introduced in 802.11n, as well as the architecture, design trade-offs, and implementation details of a two spatial stream CMOS 802.11n-draft-compliant SoC.

A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC

The rapid commercialization of the IEEE 802.11n WLAN standard has increased the demand for higher data-rate and longer-range fully integrated MIMO SoCs that are backward-compatible with legacy IEEE 802.11a/b/g networks. This paper introduces a 3-stream, 3×3 MIMO WLAN SoC that utilizes three antennas to improve throughput, range, and link robustness. This chip integrates three dual-band transceivers, digital physical layer, media access controller, and a PCI express interface in a 65nm CMOS process. Improved EVM is achieved by reducing transmit and receive I/Q mismatch with calibration, and reducing the integrated phase noise with a reference clock doubler.

A single-chip CMOS bluetooth v. 2.1 radio SoC

A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced Data Rates is implemented in standard 0.13 mum CMOS technology. All functions of a Bluetooth radio are integrated in the SoC, including RF, analog and digital parts. The RF transceiver features a polar transmitter, a two-point modulated fractional-N synthesizer, a 500 kHz IF receiver with first order low-pass analog filtering, and a DeltaSigma ADC with 74 dB dynamic range. The total SoC die area is 9.2 mm2 with only 3.0 mm2 for analog and RF circuits. The basic-rate radio power consumption is below 30 mA for both receive and transmit.