Srenik Mehta

A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems

A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-/spl mu/m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure and -112-dBc/Hz synthesizer phase noise at 1-MHz frequency offset.

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output.

An 802.11g WLAN SoC

A single-chip IEEE 802.11g-compliant WLAN radio that implements all RF, analog, and digital PHY and MAC functions is implemented in a 0.18 /spl mu/m CMOS technology. The IC transmits 4 dBm EVM-compliant output power for a 64QAM OFDM signal. The overall receiver sensitivities are -95 dBm and -73 dBm for data rates 6 Mbit/s and 54 Mbit/s, respectively.

A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC

Digital Phase-Locked Loops (DPLLs), which are amenable to CMOS process scaling, have recently been demonstrated for both wireless and wireline applications as alternatives to conventional analog charge-pump based PLLs [1–4]. This paper presents a calibration-free fractional-N DPLL that uses only an integer-N divider with a time-to-digital converter (TDC) embedded inside the VCO and utilizes a mismatch filtering technique to improve the linearity of the TDC.

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g WLAN

A 2.4/5 GHz transceiver implements the RF and analog front-end of an IEEE 802.11a/g/b WLAN system in 0.25 /spl mu/m CMOS technology. The IC transmits 9 dBm/8 dBm EVM-compliant output power at 5 GHz/2.4 GHz for a 64QAM OFDM signal. The overall receiver NF is 5.5/4.5 dB at 5/2.4 GHz.

A 5 GHz CMOS transceiver for IEEE 802.11a wireless LAN

A 5 GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-complaint WLAN using a 0.25 /spl mu/m CMOS technology occupies 22 mm/sup 2/. The IC has 22 dBm maximum transmitted power, 8 dB overall receive-chain noise figure, and -112 dBc/Hz synthesizer phase noise at 1 MHz offset.

A single-chip CMOS direct-conversion transceiver for 900 MHz spread-spectrum digital cordless phones

This fully-integrated transceiver incorporates RF circuits, synthesizer, baseband filters, demodulator, and digital signal processing. The few off-chip components include an ISM band filter, a balun, an RF matching network, an RC loop filter for the PLL, a crystal resonator, and a resistor for biasing. A transmit/ receive (T/R) switch is avoided by sharing a single RF port between transmitter and receiver. An offset cancellation method attenuates offsets in the baseband without sacrificing bandwidth in the direct conversion receiver. Careful circuit design, timing, and layout considerations provide isolation between the sensitive RF signals and the digital switching noise. The IC is in 0.6/spl mu/m CMOS and provides a complete interface between antenna and voiceband codec.

A CMOS dual-band tri-mode chipset for IEEE 802.11a/b/g wireless LAN

This paper presents the design of a dual-band, tri-mode wireless LAN chipset for IEEE 802.11a/b/g. The chipset, designed in 0.25/spl mu/m standard CMOS, features a 5GHz RF transceiver, a 2.4GHz RF transceiver, and a baseband processor with media access controller. The overall design achieves a measured sensitivity of at least -70dBm at 54Mbps and -92dBm at 6Mbps for IEEE 802.11a/g as well as -94dBm at 1Mbps for 802.11b.

A 1.9GHz Single-Chip CMOS PHS Cellphone

A single-chip CMOS PHS cellphone, fabricated in a 0.18mum CMOS process, implements all handset functions including radio, voice, audio, CPU, and digital interfaces. The IC has +4dBm EVM-compliant transmit power, -106dBm receiver sensitivity, and 15mus synthesizer settling time. It draws 81 mA from a 1.8V supply while occupying 35mm2 of chip area

Design and implementation of a CMO 802.11n SoC

Wireless local area networks based on the IEEE 802.11 standard are rapidly replacing wires within homes and offices. The latest data-rate amendment to the IEEE 802.11 standard, known as the 802.11n, provides enhanced user experience by exploiting MIMO techniques that use multiple antennas for both transmitter and receiver. In conjunction with MAC layer improvements such as aggregating data, the 802.11n standard supports PHY data rates as high as 600 Mb/s with four spatial streams. This article discusses various MAC and PHY level modifications introduced in 802.11n, as well as the architecture, design trade-offs, and implementation details of a two spatial stream CMOS 802.11n-draft-compliant SoC.