Susan Luschas

Radio frequency digital-to-analog converter

Dynamic performance of high-speed high-resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization, and clock jitter are all culprits. A DAC output controlled by an oscillating waveform is proposed to mitigate the effects of switching distortion and clock jitter. This architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency, allowing a high-frequency image of the input to be used as the output. This has the potential for better noise performance and power and hardware savings relative to a conventional DAC+mixer architecture. A narrow-band sigma-delta (/spl Sigma//spl Delta/) DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept in a 1.8-V 0.18-/spl mu/m CMOS technology. Measured single-tone SFDR is -75 dBc, SNR is 53 dB, and two-tone IMD3 is -70.8 dBc for a 17.5-MHz band centered at 942 MHz. SNR performance is shown to have the predicted dependence on the phase alignment of the data clock and oscillating pulse.

Output impedance requirements for DACs

Communications applications are driving the development of high output frequency digital to analog converters (DACs) with tough SNR and SFDR frequency-domain specifications. Static measures of performance such as INL and DNL are becoming irrelevant. This paper derives and compares the output impedance required for a DAC to meet static and dynamic specifications in both single-ended and fully-differential implementations. It is shown that the output impedance required in a fully-differential implementation is much lower than that required in a single-ended one. This reduced output impedance requirement has the potential to eliminate traditional impedance-boosting cascode transistors, allowing DACs to scale with technology to reduced supply voltages.

High-speed /spl Sigma//spl Delta/ modulators with reduced timing jitter sensitivity

As higher and higher frequency signals are sampled, clock jitter limits the achievable signal-to-noise ratio (SNR) in an analog-to-digital converter (ADC). This clock jitter limit is reviewed for upfront sampled ADCs and continuous-time (CT) sigma-delta modulators (/spl Sigma//spl Delta/Ms). A pulse-shaped feedback digital-to-analog converter (DAC) is proposed to mitigate the jitter-imposed SNR limit in CT /spl Sigma//spl Delta/Ms. An intuitive analysis that compares the pulse-shaped DAC to conventional DACs is presented. This analysis as well as a more rigorous analysis shows that the pulse-shaped feedback /spl Sigma//spl Delta/M has potential for significant SNR improvement over conventional CT /spl Sigma//spl Delta/Ms as well as any upfront sampled system. For typical jitter, phase and amplitude noise numbers, SNR improvement is on the order of 17 dB over a conventional CT /spl Sigma//spl Delta/M and 8 dB over an upfront sampled ADC for a 1-GHz input.

A Single-Chip CMOS Radio SoC for v2.1 Bluetooth Applications

This paper presents a Bluetooth v2.1 compliant SoC that integrates all functions of a Bluetooth radio. The transceiver comprises a two-point modulated fractional-N synthesizer, a polar transmitter, and a 500 kHz IF receiver with minimal analog filtering. The radio architecture is chosen to minimize overall die area as well as power consumption for both the basic and enhanced data rates. The SoC is implemented in a standard 0.13 mum digital CMOS technology with a die area of 9.2 mm2, of which only 3.0 mm2 is occupied by the analog and RF blocks. The basic-rate radio draws a total supply current of 29.7 mA in the receive mode and 29.4 mA in the transmit mode.

A Single-Chip CMOS Bluetooth v2.1 Radio SoC

Bluetoothcopyradios are becoming pervasive in small, battery-powered devices. This is being driven by the reduced area requirements, cost, and power consumption of Bluetooth chips. As process technology scales down to 0.13 mum CMOS and beyond, the opportunities to trade off digital complexity to reduce analog requirements can enable optimized radio designs. This article presents an architecture on both the transmitter and receiver that can optimize this digital/analog trade-off while still meeting all system requirements. A polar transmitter is presented that is capable of transmitting both basic rate and enhanced data rate traffic. The low-IF receiver is also optimized, requiring very little analog filtering and using an oversampled analog- to-digital converter to move the filtering burden to the digital domain. The result is the smallest and lowest power Bluetooth radio published to date.

A 1.9GHz Single-Chip CMOS PHS Cellphone

A single-chip CMOS PHS cellphone, fabricated in a 0.18mum CMOS process, implements all handset functions including radio, voice, audio, CPU, and digital interfaces. The IC has +4dBm EVM-compliant transmit power, -106dBm receiver sensitivity, and 15mus synthesizer settling time. It draws 81 mA from a 1.8V supply while occupying 35mm2 of chip area

A 1.9-GHz Single-Chip CMOS PHS Cellphone

A single-chip CMOS PHS cellphone, integrated in a 0.18-mum CMOS technology, implements all handset functions including radio, voice, audio, MODEM, TDMA controller, CPU, and digital interfaces. Both the receiver and transmitter are based on a direct conversion architecture. The RF transceiver achieves -106 dBm receive sensitivity and +4 dBm EVM-compliant transmit power. The local oscillator, based on a sigma-delta fractional-N synthesizer, has a phase noise of -118 dBc/Hz at 600kHz offset and settling time of 15 mus. The current consumption for the receiver, transmitter and synthesizer are 32 mA, 29 mA, and 25 mA, respectively, from a 3.0 V supply

A 942 MHz output, 17.5 MHz bandwidth, -70dBc IMD3 /spl Sigma//spl Delta/ DAC

A DAC output controlled by an oscillating waveform is proposed to mitigate the effects of switching distortion and clock jitter. This architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency, allowing a high frequency image of the input to be used as the output. This saves power and hardware relative to a conventional transmitter architecture by eliminating the need for mixers and intermediate frequencies. The concept is demonstrated in a 1.8 V, 0.18 /spl mu/m CMOS technology. The measured single-tone SFDR is 75 dB, SNR is 52 dB, and two-tone IMD3 is -70.8 dBc for a 17.5 MHz band centered at 942 MHz.

A single-chip CMOS bluetooth v. 2.1 radio SoC

A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced Data Rates is implemented in standard 0.13 mum CMOS technology. All functions of a Bluetooth radio are integrated in the SoC, including RF, analog and digital parts. The RF transceiver features a polar transmitter, a two-point modulated fractional-N synthesizer, a 500 kHz IF receiver with first order low-pass analog filtering, and a DeltaSigma ADC with 74 dB dynamic range. The total SoC die area is 9.2 mm2 with only 3.0 mm2 for analog and RF circuits. The basic-rate radio power consumption is below 30 mA for both receive and transmit.