Guk-Hyon Yon

Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65 nm Technology Nodes

Plasma doping and laser annealing are successfully integrated into the conventional p-metal–oxide–silicon field effect transistor (PMOSFET) process to form ultra shallow junction (USJ). Comparing with the conventional combination of ion implantations and rapid thermal annealing (RTA), junction depth (XJ) and sheet resistance (RS) are reduced. Also, significant improvement of the short channel effects without the degradation of on-current is observed.

Interface states as an active component for 20 nm gate-length planar MOSFET with electrostatic channel extension (ESCE)

Electrostatic channel extension (ESCE) MOSFET, a transistor with static inversion layer formed by interface fixed charge is fabricated in planar bulk structure down to 20 nm gate-length. The 24 nm gate-length ESCE transistor with current 80 nm gate-length SRAM technology shows the excellent drive currents of 1.0 mA/mum with IOFF of 93 nA/mum at VDS = 1 V. Moreover, the ESCE transistor with the gate oxide thickness of 10 Aring shows effectively suppressed gate-oxide leakage, very low GIDL, high breakdown voltage (> 6 V), immunity from CD variance, and robust reliability. The ESCE scheme is very promising to overcome the scale-down limit of planar transistor beyond 20 nm with ultra-low cost

Integration of Sub-melt Laser Annealing on Metal Gate CMOS Devices for Sub 50 nm Node DRAM

We report on the integration of sub-melt laser spike annealing (LSA) on W-gate stacked DRAM. We applied the LSA as a reactivation in back-end processes to comply with the considerable metal-pattern effects and strong DRAM thermal-budget. Improvements in drive currents of peripheral transistors (4 %/14 % for n/p-FETs) are achieved by using the LSA without incurring short channel effect (SCE) while minimizing pattern effects of metal gate. DRAM cell transistors also show improvements in drive current, junction leakage, and GIDL (gate-induced drain leakage) without laser-induced local defects and reliability degradation

Elimination of surface state induced edge transistors in high voltage NMOSFETs for flash memory devices

Abstract The abnormal leakage failure in high voltage NMOSFETs is investigated by measuring the subthreshold hump characteristics. Gated diode, width and substrate bias dependence of the I D -V GS characteristics, and two-terminal I-V measurements between the source and the drain reveal that the hump characteristic is caused by the surface states, not by the gate field crowding at STI edges. The numerical calculation shows that the high voltage NMOSFETs are very delicate to leakage failure by a small amount of surface state (∼10 11 /cm 2 ), due to the thick gate oxide and very low doping concentration for high voltage operation (>25 V). A thermal oxidation with the thickness of 1.0 nm successfully eliminates the parasitic corner transistors without changing electrical characteristics of the targeted transistors in current state of the art flash memory devices.

Issues of Ultrashallow Junction for Sub-50 nm Gate Length Transistors: Metrology, Dopant Loss, and Novel Electrostatic Junction

Issues of ultrashallow junctions (USJ) for sub-50 nm gate-length transistors are discussed. To measure the actual current drivability of source/drain extension (SDE), we developed SDE sheet resistance test structure (SSTS) which simulates the actual geometry and thermal condition of dopant underneath sidewall spacer. By using low energy electron induced X-ray emission spectrometry (LEXES) and other conventional techniques such as four point probe (FPP) and secondary ion mass spectrometry (SIMS), we quantified SDE dopant loss during the CMOS process and found that the wet-etching removal and outdiffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively. Novel junction structures with electrostatic channel extension (ESCE) MOSFET for sub-20 nm gate-length transistor are presented as well

The P-SOG filling Shallow Trench Isolation technology for sub-70 nm device

A novel Polysilazane-based inorganic Spin-On-Glass filling Shallow Trench Isolation (P-SOG filling STI) technology is developed for sub-70 nm devices, for the first time. A key processing step of this P-SOG filling STI technology is annealing after a CMP process. The post-CMP P-SOG annealing eliminates a field oxide recess problem. This technology shows good electrical characteristics compared with a HDP oxide filling STI. The P-SOG filling STI is a promising candidate for the future isolation technology.