Soogine Chong

Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage

We present a hybrid nanoelectromechanical (NEM)/CMOS static random access memory (SRAM) cell, in which the two pull-down transistors of a conventional CMOS six transistor (6T) SRAM cell are replaced with NEM relays. This SRAM cell utilizes the infinite subthreshold slope and hysteretic properties of NEM relays to dramatically increase the cell stability compared to the conventional CMOS 6T SRAM cells. It also utilizes the zero off-state leakage of NEM relays to significantly decrease static power dissipation. The structure is designed so that the relatively long mechanical delay of the NEM relays does not result in performance degradation. Circuit simulations are performed using a VerilogA model of a NEM relay. Compared to a 65nm CMOS 6T SRAM cell, when 10nm-gap NEM relays (pull-in voltage = 0.8V, pull-out voltage = 0.2V, on resistance = 1ki2) are integrated, hold and read static noise margin (SNM) improve by ~110% and ~250%, respectively. In addition, static power dissipation decreases by ~85%. The write delay decreases by ~60%, while read delay decreases by ~10%. The advantages in SNM and static power dissipation are expected to increase with scaling.

Efficient FPGAs using nanoelectromechanical relays

Nanoelectromechanical (NEM) relays are promising candidates for programmable routing in Field-Programmable-Gate Arrays (FPGAs). This is due to their zero leakage and potentially low on-resistance. Moreover, NEM relays can be fabricated using a low-temperature process and, hence, may be monolithically integrated on top of CMOS circuits. Hysteresis characteristics of NEM relays can be utilized for designing programmable routing switches in FPGAs without requiring corresponding routing SRAM cells. Our simulation results demonstrate that the use of NEM relays for programmable routing in FPGAs can simultaneously provide 43.6% footprint area reduction, 37% leakage power reduction, and up to 28% critical path delay reduction compared to traditional SRAM-based CMOS FPGAs at the 22nm technology node.

Analytical ballistic theory of carbon nanotube transistors: Experimental validation, device physics, parameter extraction, and performance projection

We developed a fully analytical ballistic theory of carbon nanotube field effect transistors enabled by the development of an analytical surface potential capturing the temperature dependence and gate and quantum capacitance electrostatics. The analytical ballistic theory is compared to the experimental results of a ballistic transistor with good agreement. The validated analytical theory enables intuitive circuit design, provides techniques for parameter extraction of the bandgap and surface potential, and elucidates on the device physics of drain optical phonon scattering and its role in reducing the linear conductance and intrinsic gain of the transistor. Furthermore, a threshold voltage definition is proposed reflecting the bandgap-diameter dependence. Projections for key analog and digital performances are discussed.

Integration of nanoelectromechanical (NEM) relays with silicon CMOS with functional CMOS-NEM circuit

This paper demonstrates electrical results of an integrated Si CMOS-electrostatically actuated nanoelectromechanical (NEM) relay circuit. This is an initial step towards realizing previously proposed NEM-CMOS hybrid circuits that predict various benefits compared to CMOS-only circuits. In this work, an e-beam patterned laterally actuated Pt NEM relay is fabricated at CMOS-compatible temperatures (≤ 400 °C) on top of CMOS and is driven by an on-chip CMOS inverter at VDD = 6 V.

Combinational Logic Design Using Six-Terminal NEM Relays

This paper presents techniques for designing nanoelectromechanical relay-based logic circuits using six-terminal relays that behave as universal logic gates. With proper biasing, a compact 2-to-1 multiplexer can be implemented using a single six-terminal relay. Arbitrary combinational logic functions can then be implemented using well-known binary decision diagram (BDD) techniques. Compared to a CMOS-style implementation using four-terminal relays, the BDD-based implementation can result in lower area without major impact on performance metrics such as delay, and energy (when the relays are scaled to small dimensions). Although it is possible to implement any combinational circuit with a single mechanical delay, the relay count can be significantly reduced for complex logic functions by allowing multiple mechanical delays.

Nanoelectromechanical relays with decoupled electrode and suspension

This paper reports on the modeling, fabrication, and testing of cantilever- and parallel plate-based laterally actuated platinum-coated polysilicon nanoelectromechanical (NEM) relays. The polysilicon acts as the structural layer, while the platinum serves as a conducting contact material, as well as a local routing layer. The two-part cantilever design utilizes a source made of a compliant beam in series with a stiff bridged perimeter electrode to reduce the secondary pull-in of the source to the gate. The parallel-plate-based relay also uses stiffened electrodes in addition to serpentine structures that reduce the actuation voltage. Overdrive gate voltage in excess of 100% without failure and sharp release of the relay from output are achieved for polysilicon relays with 50nm platinum coating and 500nm actuation gap.

Integration of Nanoelectromechanical Relays With Silicon nMOS

Electrostatically actuated nanoelectromechanical (NEM) relays are integrated with silicon nMOS devices. An nMOSFET successfully drives a NEM relay with the MOSFET serving as a pass transistor to control the state of the relay. Silicon MOSFET-NEM relay integration opens up the possibility for applications, where the zero off-state leakage, the sharp on/off transition, and/or the hysteresis of the NEM relay can be used to complement the capabilities of CMOS.

Nano-electro-mechanical relays for FPGA routing: experimental demonstration and a design technique

Nano-Electro-Mechanical (NEM) relays are excellent candidates for programmable routing in Field Programmable Gate Arrays (FPGAs). FPGAs that combine CMOS circuits with NEM relays are referred to as CMOS-NEM FPGAs. In this paper, we experimentally demonstrate, for the first time, correct functional operation of NEM relays as programmable routing switches in FPGAs, and their programmability by utilizing hysteresis properties of NEM relays. In addition, we present a technique that utilizes electrical properties of NEM relays and selectively removes or downsizes routing buffers for designing energy-efficient CMOS-NEM FPGAs. Simulation results indicate that such CMOS-NEM FPGAs can achieve 10-fold reduction in leakage power, 2-fold reduction in dynamic power, and 2-fold reduction in area, simultaneously, without application speed penalty when compared to a 22nm CMOS-only FPGA.

Dual sidewall lateral nanoelectromechanical relays with beam isolation

Laterally actuated nanoelectromechanical (NEM) relays are implemented using a polysilicon structural layer with hafnium oxide (HfO2) and platinum dual sidewall layers. Atomic layer deposition (ALD) HfO2 provides electrical isolation between the polysilicon beam structure and the sputtered platinum conductive channel. Dual sidewall devices are demonstrated using a Y-shaped device with two contacts that connect source and drain upon actuation. Fabricated devices show up to 1µA current passing between source and drain without beam current flow, confirming successful isolation.

Technology Projection Using Simple Compact Models

We review recent efforts to capture the device non- i dealities for circuit-level technology projection for Si CMOS. We also give some examples of simple compact model development for assessing the circuit-level performance of exploratory devices such as III-V FET, carbon nanotube transistor, and nanoelectromechanical (NEM) transistors and relays.