Roozbeh Parsa

Design Considerations for Complementary Nanoelectromechanical Logic Gates

The operation and performance of complementary nanoelectromechanical (CNEM) logic gates are investigated. NEMS structures featuring dimensions 2 to 3 orders of magnitude smaller than the present MEMS relays are considered. Various metals are benchmarked to silicon as the cantilever beam material. We show that the CNEM inverters featuring laterally actuated beams, 10 nm gap and low density materials such as Si or Al can achieve nanosecond pull-in delay and sub-0.1 fJ switching energy at VDD = 1.5 V while occupying an area as small as 0.03 mum2.

Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage

We present a hybrid nanoelectromechanical (NEM)/CMOS static random access memory (SRAM) cell, in which the two pull-down transistors of a conventional CMOS six transistor (6T) SRAM cell are replaced with NEM relays. This SRAM cell utilizes the infinite subthreshold slope and hysteretic properties of NEM relays to dramatically increase the cell stability compared to the conventional CMOS 6T SRAM cells. It also utilizes the zero off-state leakage of NEM relays to significantly decrease static power dissipation. The structure is designed so that the relatively long mechanical delay of the NEM relays does not result in performance degradation. Circuit simulations are performed using a VerilogA model of a NEM relay. Compared to a 65nm CMOS 6T SRAM cell, when 10nm-gap NEM relays (pull-in voltage = 0.8V, pull-out voltage = 0.2V, on resistance = 1ki2) are integrated, hold and read static noise margin (SNM) improve by ~110% and ~250%, respectively. In addition, static power dissipation decreases by ~85%. The write delay decreases by ~60%, while read delay decreases by ~10%. The advantages in SNM and static power dissipation are expected to increase with scaling.

Efficient FPGAs using nanoelectromechanical relays

Nanoelectromechanical (NEM) relays are promising candidates for programmable routing in Field-Programmable-Gate Arrays (FPGAs). This is due to their zero leakage and potentially low on-resistance. Moreover, NEM relays can be fabricated using a low-temperature process and, hence, may be monolithically integrated on top of CMOS circuits. Hysteresis characteristics of NEM relays can be utilized for designing programmable routing switches in FPGAs without requiring corresponding routing SRAM cells. Our simulation results demonstrate that the use of NEM relays for programmable routing in FPGAs can simultaneously provide 43.6% footprint area reduction, 37% leakage power reduction, and up to 28% critical path delay reduction compared to traditional SRAM-based CMOS FPGAs at the 22nm technology node.

Nanoelectromechanical relays with decoupled electrode and suspension

This paper reports on the modeling, fabrication, and testing of cantilever- and parallel plate-based laterally actuated platinum-coated polysilicon nanoelectromechanical (NEM) relays. The polysilicon acts as the structural layer, while the platinum serves as a conducting contact material, as well as a local routing layer. The two-part cantilever design utilizes a source made of a compliant beam in series with a stiff bridged perimeter electrode to reduce the secondary pull-in of the source to the gate. The parallel-plate-based relay also uses stiffened electrodes in addition to serpentine structures that reduce the actuation voltage. Overdrive gate voltage in excess of 100% without failure and sharp release of the relay from output are achieved for polysilicon relays with 50nm platinum coating and 500nm actuation gap.

Nano-electro-mechanical relays for FPGA routing: experimental demonstration and a design technique

Nano-Electro-Mechanical (NEM) relays are excellent candidates for programmable routing in Field Programmable Gate Arrays (FPGAs). FPGAs that combine CMOS circuits with NEM relays are referred to as CMOS-NEM FPGAs. In this paper, we experimentally demonstrate, for the first time, correct functional operation of NEM relays as programmable routing switches in FPGAs, and their programmability by utilizing hysteresis properties of NEM relays. In addition, we present a technique that utilizes electrical properties of NEM relays and selectively removes or downsizes routing buffers for designing energy-efficient CMOS-NEM FPGAs. Simulation results indicate that such CMOS-NEM FPGAs can achieve 10-fold reduction in leakage power, 2-fold reduction in dynamic power, and 2-fold reduction in area, simultaneously, without application speed penalty when compared to a 22nm CMOS-only FPGA.

Dual sidewall lateral nanoelectromechanical relays with beam isolation

Laterally actuated nanoelectromechanical (NEM) relays are implemented using a polysilicon structural layer with hafnium oxide (HfO2) and platinum dual sidewall layers. Atomic layer deposition (ALD) HfO2 provides electrical isolation between the polysilicon beam structure and the sputtered platinum conductive channel. Dual sidewall devices are demonstrated using a Y-shaped device with two contacts that connect source and drain upon actuation. Fabricated devices show up to 1µA current passing between source and drain without beam current flow, confirming successful isolation.

2D analytical model for the study of NEM relay device scaling

NEM relay is a promising class of device to overcome the power crisis of CMOS circuits. To design these devices and predict their scaling properties, an analytical model highlighting the fundamental physics of the relay operation is highly desired. This work presents a new 2D analytical model for the study of NEM relay scaling. The model retains the physical insights for NEM relays and yet has the simplicity close to the commonly used 1D model. The error as compared to a finite element model is reduced from ∼25% (1D model) to ∼3% (this work) by introducing a ratio R(a) to account for 2D effects in the 1D formulation. Besides the fundamental mechanical and electrical properties, the model also takes into account surface forces in the operation of NEM relay devices. The impact of surface forces on the operation voltage as devices are scaled down is discussed.

Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing

Nano-Electro-Mechanical (NEM) relays are nano-scale switches that can be mechanically actuated by an electrical signal. Unlike conventional CMOS transistors, NEM relays exhibit zero off-state leakage and very sharp on-off transitions. As a result, NEM relays can be potentially used to design highly energy-efficient digital systems. NEM relays are also excellent candidates for programmable routing switches in Field Programmable Gate Arrays (FPGAs) due to their potentially low on-state resistances despite their long mechanical delays. Low-temperature fabrication of NEM relays creates opportunities for their integration on top of silicon CMOS circuits. Hysteresis properties of NEM relays can enable their use as FPGA programmable routing switches without requiring additional routing SRAM cells. In this talk, we will present an overview of NEM relays and their use in digital system design, and discuss design considerations for hybrid CMOS-NEM FPGAs.