Soon Il Yeo

Design of 32 bit Parallel Processor Core for High Energy Efficiency using Instruction-Levels Dynamic Voltage Scaling Technique

This paper describes design of high energy efficiency 32 bit parallel processor core using instruct- tion-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and swit- ching activity of the function units in the proposed data technique. We present instruction-levels DVS tech- nique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage sche- duler controlled by the operation system and a hard- ware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS tech- nique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit pa- rallel processor core can utilize as the coprocessor processing massive data at high speed.

Design of high energy efficiency 32bit processing unit using instruction-levels data gating and dynamic voltage scaling techniques

This paper describes design and circuit simulation of the high energy efficiency 32bit processing unit (PU) using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating and DVS technique. We can control activation and switching activity of the function units using the proposed data gating technique and we can control powers of the function units using the proposed DVS technique. We simulated the power and circuit simulation for running test program using Spectra with layout extraction data which does not include PAD. We selected the optimum reduced power supply to 0.667 times of the supplied power supply in this paper. The energy efficiency of the proposed 32bit processing unit using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32bit processing unit without using instruction-levels data gating and DVS techniques. The energy efficiency of the proposed instruction-level DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system but a hardware implementation is very easy. The designed high energy efficiency 32bit processing unit can utilize as the coprocessor processing massive data at high speed.