Sophia Arnauts

Evaluation of megasonic cleaning for sub-90-nm technologies

Cleaning of nanoparticles (< 50nm ) is becoming a major challenge in semiconductor manufacturing and the future use of traditional methods, such as megasonic cleaning, is questioned. In this paper the capability of megasonic cleaning to remove nanoparticles without inflicting damage to fragile structures is investigated. The role of dissolved gas in cleaning efficiency indicates that cavitation is the main cleaning mechanism. Consequently gas mass-balance analyses are needed to optimize the performance of cleaning tools. When gas is dissolved in the cleaning present tools can remove nanoparticles down to about 30 nm using dilute chemistries at low temperature. Ultimate performance is limited by cleaning uniformity, which depends on tool design and operation. However no tool reached the target of high particle removal efficiency andlow damage. Significantly lower damage could only be obtained by decreasing the power, at the cost of a lower cleaning efficiency for nanoparticles. The development of damage-free megasonic is discussed.

Challenges with Respect to High-k/Metal Gate Stack Etching and Cleaning

Novel high-k gate dielectrics (HK), often Hf-based oxides, are considered for the 45 nm node and beyond to allow further scaling of the gate dielectric. In order to prevent Fermi-level pinning, metal gates (MG) with the proper work function have to be used on the high-k dielectrics. These can be implemented in a Dual MG approach [1] where thin metal layers are inserted between the high-k and the poly-Si electrode during gate stack formation (see Figure 1 left). In addition, the work function can be further tuned through high-k cap layers in high-k cap inserted CMOS (see Figure 1 right) [2,3]. Other options are ‘metal gate last’ schemes where a dummy poly-Si gate is replaced by metal after formation of the NMOS and PMOS on the wafer or, alternatively, if Fully Silicided (FUSI) gates are used (see Figure 2).

Aging phenomena in the removal of nano-particles from Si wafers

With the continuous shrinkage of critical sizes in semiconductor manufacturing, nano-particles smaller than 100-nm are becoming a potential threat to devices in chips. Storage of wafers contaminated during process steps often results in a decrease of particle removal efficiency in subsequent clean, a phenomenon referred to as aging. In this work, the influence of aging on the removal of silica and silicon nitride nano-particles from hydrophilic Si wafers was studied for different storage conditions. Trends observed for aging as a function of particle size and for different tools indicated that aging will become an issue for critical cleans where substrate etching must be kept very low and the physical component of the clean must be decreased to prevent damage to fine structures. Controlling the relative humidity during storage helped in lowering the effect of aging.

Wet Chemical Cleaning of InP and InGaAs

In this work, the compatibility of InP and InGaAs in cleaning solutions commonly used in semiconductor manufacturing is investigated. Aqueous oxidizing cleans should be avoided as the substrates dissolve rapidly. Low pH solutions may impose some serious ES&H issues due to hydride evolution occurring upon acidic hydrolysis of the III-V material. However, acidic solutions are very efficient to remove the native oxide from the substrate. Complete oxide free surfaces are not achieved after wet cleaning due to the rapid oxidation of these materials in the atmosphere.

Ex Situ Bubble Generation, Enhancing the Particle Removal Rate for Single Wafer Megasonic Cleaning Processes

Introduction In a megasonic cleaning process, which focuses on sub 100nm sized particle removal, the control of transient gaseous heterogeneous cavitation becomes the primary goal [1-3]. To optimize this kind of cavitation, a good control of the local acoustical field should be obtained and as many nucleation events leading to cavitation should be present. This means that high concentrations of gaseous bubbles, either created in-situ or ex-situ the acoustical field as outlined in Figure 1, should be present near the substrate. Depending on the size of the bubbles and the local acoustic power, the cavitation can be stable or transient leading to effects as shock waves, microstreaming and water jets able to clean the substrate of interest. Earlier was shown that the presence of bubbles has a negative effect on cleaning in megasonic tank systems as the bubbles are attenuating the acoustical signal leading to cleaning non-uniformities over the wafer. In the case of a single wafer tool, as shown in this paper, the opposite effect is observed: ex-situ formed bubbles can easily be introduced in the acoustical field since transducer and substrate are close to each other and creating a unique opportunity for process optimisation. The single wafer systems described in this paper are the SONOSYS nozzle systems of 1, 2 and 3MHz.

Cleaning Challenges and Solutions for Advanced Technology Nodes

Trends in further scaled CMOS technologies are reviewed with respect to the implications for cleaning and wet processing. Particularly the FEOL processes are being considered such as selective cap removal, pre-epi cleaning and post I/I photo resist removal. For technologies beyond the 15nm Ge and III-V are being considered. Several aspects of wet processing of these materials and advanced integration schemes are covered.

Nanoscale Etching and Reoxidation of InAs

At present, the performance enhancement for Si-based transistors can no longer be guaranteed due to intrinsic mobility issues. The considerably higher electron mobility of III-V compound semiconductors (e.g. InGaAs, InAs, InSb) has led to renewed interest and a following phase in the development of future transistors for the 7-5 nm technology node [1].

Study of the Dynamics of Local Particle Removal Efficiencies Using Localized Haze Maps

The local particle removal efficiency (PRE) of nano particles in megasonic cleaning experiments is studied. This approach makes it possible to quantify non uniform cleaning effects over the wafer and to look into the dynamics of particle removal at different areas on the wafer. A direct correlation between PRE and megasonic induced damage of device structures demonstrates that a considerable amount of damage is already formed at less efficiently cleaned areas of the wafer.

Performance of a Linear Single Wafer IPA Vapour Based Drying System

In this paper, a single wafer linear IPA vapour based vertical drying technique is presented. Using salt residue tests the performance of this technique is evaluated and compared to spin drying. The equivalent film thickness of evaporating liquid is below 0.05µm for blanket wafers, which is two orders of magnitude less than with spin drying. It is also shown that the presence of surface topography (200nm high TEOS features on Si covered with a chemical oxide) does not significantly influence the drying performance. A study of the process window shows that for the setup evaluated in this work best performance is achieved when the IPA/N2 flow rate is above 20 liters per minute and the drying speed is below 8 mm/s. With a manual prototype already very good particle performance is demonstrated.

Nanoscale Etching of GaAs and InP in Acidic H2O2 Solution: A Striking Contrast in Kinetics and Surface Chemistry

In this study of nanoscale etching for state-of-the-art device technology the importance of the nature of the surface oxide, is demonstrated for two III-V materials. Etching kinetics for GaAs and InP in acidic solutions of hydrogen peroxide are strikingly different. GaAs etches much faster, while the dependence of the etch rate on the H+ concentration differs markedly for the two semiconductors. Surface analysis techniques provided information on the surface composition after etching: strongly non-stoichiometric porous (hydr)oxides on GaAs and a thin stoichiometric oxide that forms a blocking layer on InP. Reaction schemes are provided that allow one to understand the results, in particular the important difference in etch rate and the contrasting role of chloride in the dissolution of the two semiconductors.