Daniel Cuypers

Electrochemical Deposition of Subnanometer Ni Films on TiN

In this paper, we show the electrochemical deposition of a subnanometer film of nickel (Ni) on top of titanium nitride (TiN). We exploit the concept of cluster growth inhibition to enhance the nucleation of new nuclei on the TiN substrate. By deliberately using an unbuffered electrolyte solution, the degree of nucleation is enhanced as growth is inhibited more strongly. This results in a very high particle density and therefore an ultralow coalescence thickness. To prevent the termination of Ni deposition that typically occurs in unbuffered solutions, the concentration of Ni(2+) in solution was increased. We have verified with RBS and ICP-MS that the deposition of Ni on the surface in this case did not terminate. Furthermore, annealing experiments were used to visualize the closed nature of the Ni film. The closure of the deposited film was also confirmed by TOF-SIMS measurements and occurs when the film thickness is still in the subnanometer regime. The ultrathin Ni film was found to be an excellent catalyst for carbon nanotube growth on conductive substrates and can also be applied as a seed layer for bulk deposition of a smooth Ni film on TiN.

Study of the Etching Mechanism of Heavily Doped Si in HF

Following Moores scaling law, the transistor source and drain area become shallower and higher doped regions. As a consequence the limitations of substrate and dopant loss during cleaning become more stringent. For a better understanding, highly B, As and P doped blanket substrates, either prepared by ion implantation or by EPI growth, are studied. Substrate and dopant loss as a function of time and different HF etching conditions is monitored by Inductively Coupled Plasma Mass Spectrometry (ICP-MS) and additional techniques like Spectroscopic Ellipsometry (SE), .... It is shown that in general, the Si etching is dependent of the position of the Fermi level. More remarkably, the junction (4 nm) of a non-annealed heavily As or P doped substrate is completely removed after less than 20 min of etching in HF. This process is related to enhanced etch rates because of the amorphization of the substrate.

Cleaning Challenges and Solutions for Advanced Technology Nodes

Trends in further scaled CMOS technologies are reviewed with respect to the implications for cleaning and wet processing. Particularly the FEOL processes are being considered such as selective cap removal, pre-epi cleaning and post I/I photo resist removal. For technologies beyond the 15nm Ge and III-V are being considered. Several aspects of wet processing of these materials and advanced integration schemes are covered.

Cleaning of III-V Materials: Surface Chemistry Considerations

Compound semiconductors based on group III and V elements of the periodic system have high charge carrier mobility and are, therefore, candidates for channel material in future CMOS devices [1]. In order to design wet chemical solutions that lead to appropriate surface pre-conditioning and allow for nanoscale processing and minimal substrate loss, a thorough understanding of the interactions between the substrate and the chemical solutions is needed and the basic etching mechanisms needs to be resolved. The focus of this research is on InP in acidic solutions. ESH aspects are also considered.