Prathap Muthana

Design, Modeling, and Characterization of Embedded Capacitor Networks for Core Decoupling in the Package

Embedded passives are gaining in importance due to the reduction in size of electronic products. Capacitors pose the biggest challenge for integration in packages due to the large capacitance required for decoupling high performance circuits. Surface mount discrete (SMD) capacitors become ineffective charge providers above 100 MHz due to the increased effect of loop inductance. This paper focuses on the importance of embedded capacitors above this frequency. Modeling, measurements, and model to hardware correlation of these capacitors are shown. Design and modeling of embedded capacitor arrays for decoupling processors in the midfrequency band (100 MHz-2 GHz) is also highlighted in this paper.

Mid frequency decoupling using embedded decoupling capacitors

Surface mount technology (SMT) decoupling capacitors fail to provide decoupling above 100MHz. This paper presents the use of embedded thin film capacitors to provide decoupling in the mid frequency range from 100MHz to 2GHz. On-chip capacitance provides decoupling above 2GHz. The effect of chip, package and board capacitors on the performance of digital systems is analyzed taking into account the parasitic effects of power/ground planes, vias and solder balls. A synthesis and selection methodology for embedded package capacitors is also presented.

Improvements in Noise Suppression for I/O Circuits Using Embedded Planar Capacitors

The performance of embedded planar capacitors in noise suppression of input/output (I/O) circuits and improvements in board impedance profile have been investigated in this paper. Simultaneous switching noise (SSN) is a critical issue in todays systems and this paper shows performance improvements by introducing thin planar embedded capacitors in the board stack up. Measurement and modeling results by including the effects of transmission lines and the power ground plane pairs in the board stack up in the gigahertz range quantify the performance of the embedded capacitors.

Magnetic nanocomposites for organic compatible miniaturized antennas and inductors

Current wireless systems are limited by RF technologies in their size, communication range, efficiency and cost. RF circuits are difficult to miniaturize without compromising performance. Antennas and inductors are major impediments for system miniaturization because of the lack of magnetic materials with suitable high frequency properties. Keeping antenna and inductor requirements into consideration, two magnetic nanocomposite systems - silica coated cobalt-BCB and Ni ferrite-epoxy were investigated as candidate materials. Nanocomposite thick film structures (125-225 microns) were screen printed onto organic substrates. Parallel plate capacitors and single coil coplanar inductors were fabricated on these films to characterize the electrical and magnetic properties of these materials at low and high frequencies. Electrical characterization showed that the Co/SiO/sub 2/ nanocomposite sample has a permeability and a matching permittivity of /spl sim/10 at GHz frequency range making it a good antenna candidate. Both polymer matrix composites retain high permeability at 1-2 GHz.

Embedded decoupling capacitor performance in high speed circuits

Embedded decoupling is normally considered a better solution than surface mount decoupling for suppressing the switching noise of a high speed digital board/package because of its shorter leads that result in smaller parasitic inductance. This leads to lower impedance over a higher frequency band. It is presumably better in reliability and lowers the cost as well. Designers tend to use large value capacitors for efficient decoupling. Usually, to increase capacitance of an embedded capacitor, one can use a material with higher dielectric constant, design larger electrodes, and reduce the thickness of the dielectric. However, these strategies may sometimes lead to lower performance at high frequency band. This paper will discuss the pros and cons of different embedded capacitor approaches through simulation. As an application example, a typical power/ground network with an embedded capacitor will be compared with that of surface mount discrete capacitor.

Enhancement of Signal Integrity and Power Integrity with Embedded Capacitors in High-Speed Packages

Improvements in electrical performance of microelectronic systems can be achieved by the integration of passive elements such as capacitors, resistors and inductors. The advantage of embedded passives is their low parasitic values. In this paper, enhancement of signal-integrity and power-integrity is investigated when a high-k planar capacitor is used as a power-ground plane, with embedded high-k discrete capacitors that have low ESI and ESR values as decoupling capacitors for SSN suppression. In order to capture the effects of embedded capacitor performance, a test-structure involving many signal-lines referenced to a power-ground plane was simulated. Simulation results show that the high-k planar capacitor reduces coupling of noise currents through the power-ground planes and helps improve the eye-opening. Simulation results have been quantified for a case, where a fewer number of embedded discrete capacitors helps reduce SSN more significantly than surface-mounts. Transient co-simulation of the signal delivery network (SDN) and the power-delivery network (PDN) are performed using Y-parameters

Packaging of multi-core microprocessors: tradeoffs and potential solutions

Power consumption and interconnect latency are becoming major bottlenecks in the design of high performance computers and microprocessors. In this paper we propose to use a multicore processor approach to improve the performance of a processor. This paper discusses an analysis of the performance trade offs between single and multicore processors based on power, frequency, bandwidth and the role of embedded passives with high density wiring in future packages to support such processors.

Analysis of Embedded Package Capacitors for High Performance Components

The ever increasing power requirements of processors and application specific integrated circuits (ASICs) impose stringent requirements on the design of power distribution networks (PDNs). This paper highlights a power analysis methodology and discusses the decoupling requirements of high performance components. The advantages of embedded package capacitors in core and I/O decoupling will be highlighted

I/O Decoupling in High Speed Packages Using Embedded Planar Capacitors

Embedded passives are gaining in importance due to the reduction in size of consumer electronic products. Embedded passives are gradually replacing discretes due to the miniaturization of electronic products. Integration of these passives within the package increases the real estate for active components. This would increase the functionality of the system. Among the passives, capacitors pose the biggest challenge due to the large capacitance required for decoupling high performance circuits. This paper will highlight the performance of DuPonts planar embedded capacitor laminates in organic packages to provide I/O decoupling for active circuits.

Design, fabrication, and reliability assessment of embedded resistors and capacitors on multilayered organic substrates

Embedded passives provide a practical solution to microelectronics miniaturization. In a typical circuit, over 80 percent of the electronic components are passives such as resistors, inductors, and capacitors that could take up to 50 percent of the entire printed circuit board area. By integrating passive components within the substrate, embedded passives reduce the system real estate, eliminate the need for discrete components and assembly of same, enhance electrical performance and reliability, and potentially reduce the overall cost. Moreover, it is lead free. Even with these advantages, embedded passive technology is at a relatively immature stage and more characterization and optimization are needed for practical applications leading to its commercialization. This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on multilayered microvia organic substrate. Two test vehicles focusing on resistors and capacitors have been designed and fabricated by Packaging Research Center (PRC) and Endicott Interconnect Technologies (EI). Resistors are carbon ink based polymer thick film (PTF) and NiCrAlSi, and capacitors are made with polymer/ceramic nanocomposite material. High frequency measurement of these capacitors was performed. Furthermore, reliability assessments of thermal shock and temperature humidity tests based on JED EC standards are presented.