Stephen S. Poon

Dramatic increases in latchup holding voltage for sub-0.5 /spl mu/m CMOS using shallow S/D junctions

Large increases in the latchup holding voltage are demonstrated with the use of shallow source-drain junctions in a sub-0.5 /spl mu/m CMOS process. Holding voltages well above the supply voltage for 2 /spl mu/m n/sup +//p/sup +/ spacings are demonstrated without the use of complex processes such as retrograde wells or buried layers. SIMS data is presented to verify the reduction in junction depths to 0.15 /spl mu/m for the p/sup +//n-well and 0.14 /spl mu/m for the n/sup +//p-well junction. The improvement in holding voltage is attributed to reductions in parasitic bipolar transistor gains, due to the increase in base width. Well behaved transistor characteristics are presented using the shallow junction technology.<<ETX>>

Application of APCVD TEOS/ozone thin films in < 0.5-μm IC fabrication: trench and intermetal dielectric isolation and gap fill

Basic film and process characteristics in conjunction with electrical test results are presented showing the effect of implementing a void free oxide for both intermetal and shallow trench isolation. An integrated intermetal dielectric (IMD) process is evaluated on fully functional 0.5 micrometers BiCMOS memory circuits. The integrated process uses two different films, an oxide for gap fill deposited at atmospheric pressure (APCVD) using a TEOS/O3 chemistry, and a second oxide deposited from TEOS using plasma enhanced CVD(PETEOS) for planarization, stress management, and moisture protection. The effect of a thin PETEOS barrier between TEOS/O3 and the underlying metal is explored, and some issues concerning the integration of chemical mechanical polishing into a void free backend process flow are investigated. The suitability of undoped APCVD TEOS/O3 thin films for isolation trench fill is also characterized and described. Process variable which determine the relevant properties for trench fill are evaluated. Well-behaved MOS transistors with excellent parasitic performance were achieved using trench isolation and are reported.

Performance, standby power, and manufacturability trade-off in transistor design consideration for 0.25-μm technology

In this paper, we compare four different approaches for transistor design for the 0.25 micrometer technology from the point of view of performance, stand-by power and ease of manufacturing. For the high performance logic applications such as high end microprocessors, 0.18 micrometer transistor (Lgate equals 0.18 plus or minus 0.02 micrometer) with super steep retrograde wells and halo implants but without extension implants can achieve maximum frequency of operation (Fmax) exceeding 380 Mhz for the 0.25 micrometer technology. On the other hand, for low power applications such as mobile communication equipments, a different 0.22 micrometer (Lgate equals 0.22 plus or minus 0.02 micrometer) transistor design which simplifies manufacturing process by eliminating two photolithography steps becomes more attractive. The four transistor designs are compared using CV/I metric and manufacturability trade-offs are discussed.