Sung-jae Byun

Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage

A new type of memory, paired FinFET charge trap memory is reported. It consists of two split silicon fins and insulator between them. Two channels are formed on the outer surface of silicon so doubled integration density can be achieved. We successfully fabricated paired FinFET SONOS devices. It shows good program and erase characteristics. Independent programming on each storage nodes is demonstrated. The circuit configuration for NAND flash application is also proposed

Vertical Structure NAND flash array integration with paired FinFET multi-bit scheme for high-density NAND flash memory application

Multi-bit vertical structure NAND (VsNAND) flash memories with 32-paired FinFET cell string have been successfully integrated for the first time. Its array integration issues regarding the sub-10 nm vertical structure fin could be solved by proper choices of isolation material, ion implantation, and word line patterning. VsNAND flash array cells with TANOS (TaN/Al2O3/SiN/SiOx/Si) charge trap structure show possibilities of acceptable program/erase properties and cell Vth distribution characteristics for multi-level NAND flash application.