Sungho Jang

A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n/sup +/-doped polysilicon

Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p/sup +/ poly gate formed by BF/sub 2/ ion implanted compensation of in situ phosphorus (n/sup +/) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n/sup +/- and p/sup +/-doped WSi/sub x/-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-/spl kappa/ Al/sub 2/O/sub 3/ and HfO/sub 2/ dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability.

A 6F/sup 2/ DRAM technology in 60nm era for gigabit densities

A novel process technology for 6F/sup 2/ DRAM cell at 68nm design rule was for the first time developed. The cell size is 0.028/spl mu/m/sup 2/, which is the smallest cell size ever reported. ArF lithography with double expose technology and highly selective etching process were used for patterning of critical layers. This 6F cell was made of simple line/space patterns for easy patterning and self-aligned etches to improve process margins. MIM cell capacitor was developed with multi-layer high-k dielectric materials and 11A equivalent Tox and sub-lfA leakage was confirmed.

Highly manufacturable 4 Gb DRAM using using 0.11 /spl mu/m DRAM technology

4 Gb DRAM has been developed successfully using 0.11 /spl mu/m DRAM technology. Considering manufacturability, we have focused on developing patterning technology that makes 0.11 /spl mu/m design rules possible using KrF lithography. Also, novel DRAM technologies, which have a big influence on the future DRAM integration, are developed as follows:, using novel oxide (SOG) for the enhanced capability of gap-filling, borderless metal contact and stud processes, line-type storage node SAC, thin gate oxide, and CVD Al process for metal interconnections.

A Full FinFET DRAM Core Integration Technology Using a Simple Selective Fin Formation Technique

A full FinFET DRAM core which consists of McFETs for both the sense amplifiers and the sub-word drivers, as well as FinFETs for the memory cell array has been developed. It will efficiently shrink chip size and improve chip performance, and therefore, meet requirements for the future DRAMs with 55nm or smaller design rule. Newly developed schemes which are a selective STT SiN liner removal process, a selective TiN gate stack and narrow active pitch patterning have been successfully integrated

Highly manufacturable and high performance SDR/DDR 4 Gb DRAM

A 4 Gb SDR/DDR DRAM is fabricated with 0.11 /spl mu/m CMOS technology. To the best of our knowledge, this is the first working DRAM ever achieved at such a high density. The cell size and chip size of the 4 Gb DRAM are approximately 0.1 /spl mu/m/sup 2/ and 645 mm/sup 2/, respectively. The key technologies developed for this 4 Gb DRAM are KrF lithography with RET, novel ILD gap-filling, full SAC with LSC, novel W-BL, low-temperature Al/sub 2/O/sub 3/ MIS capacitor, and triple level CVD-Al interconnection technology. The key features of these technologies were reported elsewhere (Jeong et al., Tech. Digest of IEDM, pp. 353-6, 2000). The summary of 0.11 /spl mu/m DRAM technology is listed and compared with our previous 0.13 /spl mu/m (Kim et al., 2000) and 0.15 /spl mu/m (Kim et al., 1998) generations. We have found that random single-bit and/or twin-bit failures and block failures are the most critical issues to be solved for achieving good functionality of 4 Gb DRAM. In order to get rid of the single and twin bit failures, 80 nm array transistors, sub-80 nm memory cell contacts and mechanically robust capacitors are developed and triple-level CVD Al technology is optimized to reduce block failure as well as improve chip performance. In this paper, these technologies for achieving good functionality with high performance are highlighted in detail.

Integrated device and process technology for sub-70nm low power DRAM

A novel process technology for 70nm DRAM was for the first time developed. ArF lithography with lithography friendly layout and highly selective etching process were used for patterning of critical layers. A novel gap-fill technology using spin coating oxide was used for STI and ILD processes. Metal tungsten on dual poly gate and dual gate oxide with plasma nitridation process was used for the performance of peripheral transistors. Bar type bit line contact was used to increase the transistor current about 10%. MIM cell capacitor was developed with buried-OCS scheme and 15/spl Aring/ equivalent Tox and 1fA leakage was confirmed.

In-Depth Analysis of NBTI at 2X nm Node DRAM

An analysis on the degradation of DRAM performance caused by the NBTI degradation of p-MOSFET is first to be reported. To improve the NBTI immunity, three candidates are examined. First, minimizing Si-H bonds at Si/SiON interface through controlling the heat-budget at BEOL shows a promising result in NBTI lifetime, but it is not appropriate for DRAM process since it decreases the refresh time. Next, the buried SiGe channel p-MOSFET, which has 1.2 times higher NBTI immunity, is considered but difficult to adopt in DRAM peripheral circuit due to extra manufacturing cost. Finally, a deuterium annealing seems to be the right candidate for DRAM process since it improves the NBTI immunity without the refresh time penalty. This NBTI gain, however, varies depending on the amount of deuterium atom at Si/SiON interface and the probability of Si-D bond replacement with Si-H bond. Thus, selecting a right process sequence and an annealing condition is crucial.

70nm DRAM technology for DDR-3 application

For the first time, we developed 70nm DRAM technology applicable to a manufacturing level. This technology is aimed at DDR-3 application, which requires low-voltage operation and high speed performance. Fully working 70nm DRAMs were realized combining W-gate dual poly process, recess-channel-array-transistors (RCATs), and MIM cell capacitor module. In this paper, we present performance of 70nm node DRAMs which qualifies DDR-3 application requirement.

Lateral-Extended (LatEx.) active for improvement of data retention time for sub 60nm DRAM era

A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement was successfully achieved in 60 nm technology node DRAM by virtue of reduced source/drain area and improved subthreshold slope due to decreased cross-sectional area of top trench profile and vertical bottom trench process. In this paper, LatEx active coupled with SRCAT is proved to be suitable for sub 60 nm DRAM cell array transistor technology.

Improvement of the tail component in retention time distribution using buffered n-implantation with tilt and rotation (BNITR) for 0.2 um DRAM cell and beyond

The novel junction process scheme in DRAM memory cell with 0.2 um design rule and STI (Shallow Trench Isolation) has been investigated to improve the tail component of DRAM retention time distribution. In this paper, we propose BNITR (Buffered N-Implantation with Tilt and Rotation) process scheme that is designed on the basis of the local field-enhancement model of the tail component and report an excellent improvement effect in tail distribution of retention time without device degradation.