SungHun Cho

Accurate Sub-1 V CMOS Bandgap Voltage Reference with PSRR of -118 dB

A low voltage high PSRR CMOS Bandgap circuit capable of generating a stable voltage of less than 1 V (0.8 V and 0.5 V) robust to Process, Voltage and Temperature (PVT) variations is proposed. The high PSRR of the circuit is guaranteed by a low-voltage current mode regulator at the central aspect of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage V reg for the BG core and Op-Amp rather than the V DD . These current mirrors reduce the impact of supply voltage variations. The proposed circuit is implemented in a 0.35 ㎛ CMOS technology. The BGR circuit occupies 0.024 ㎟ of the die area and consumes 200 ㎼ from a 5 V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference achieved -118 ㏈ at frequencies up to 1 ㎑ and -55 ㏈ at 1 ㎒ without additional circuits for the curvature compensation. A temperature coefficient of 60 ppm/℃ is obtained in the range of -40 to 120℃.

A design of 10-bit, 10MS/s Pipelined ADC with Time-interleaved SAR

This paper presents a 10-bit, 10MS/s pipelined ADC with a time-interleaved SAR. Owing to the shared multiplying-DAC between the flash ADC and the multi-channel-SAR ADC, the total capacitance of the SAR ADC is decreased by 93.75%. The proposed ADC architecture can therefore provide a higher resolution than the conventional time-interleaved flash-SAR ADC. The proposed 10-bit, 10 MS/s ADC achieves a 9.318-bit ENOB and a figure-of-merit of 357.11 fJ/conversion-step. The ADC that consumes 2.28mW under a supply voltage of 1.2V was fabricated in 0.13m CMOS and occupies an area of only 0.21mm2.

A design of inductive coupling wireless power receiver with high efficiency Active Rectifier and multi feedback LDO regulator

This paper presents an inductive coupling wireless power receiver with high efficiency active rectifier and multi feedback LDO regulator. The synchronous active rectifier with the zero current sensing is proposed to achieve the high efficiency minimizing the reverse leakage current. Multi Feedback LDO regulator is proposed to implement the output voltage regulation, over voltage protection, over current limit, and adaptive communication limit sharing the single power transistor. This chip is implemented using 0.18 μm BCD technology with an active area of 4.0 mm × 4.0 mm. The maximum power conversion efficiency of the Active Rectifier is 94.2 % when the load current is 800 mA.

A 4-Channel Multi-Rate VCSEL Driver with Automatic Power, Magnitude Calibration using High-Speed Time-Interleaved Flash-SAR ADC in 0.13 ㎛ CMOS

This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using 0.13-μm CMOS technology and the die area is 4.2 mm². The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.