Keundo Ban

Positive and negative tone double patterning lithography for 50nm flash memory

Double patterning lithography is very fascinating way of lithography which is capable of pushing down the k1 limit below 0.25. By using double patterning lithography, we can delineate the pattern beyond resolution capability. Target pattern is decomposed into patterns within resolution capability and decomposed patterns are combined together through twice lithography and twice etch processes. Two ways, negative and positive, of doing double patterning process are contrived and studied experimentally. In this paper, various issues in double patterning lithography such as pattern decomposition, resist process on patterned topography, process window of 1/4 pitch patterning, and overlay dependent CD variation are studied on positive and negative tone double patterning respectively. Among various issues about double patterning, only the overlay controllability and productivity seemed to be dominated as visible obstacles so far.

Noble FeRAM technologies with MTP cell structure and BLT ferroelectric capacitors

A 16 Mb 1TIC FeRAM with a novel cell structure has been successfully developed with 0.25 /spl mu/m process technology using (Bi,La)/sub 4/Ti/sub 3/O/sub 12/ (BLT) capacitors for the first time. The developed FeRAM is highly scalable and reliable as a result of applying an MTP (merged top electrode and plate line) structure and BLT stacked capacitor, respectively.

Comparison study for 3x-nm contact hole CD uniformity between EUV lithography and ArF immersion double patterning

In order to continue scaling down the feature sizes of the devices, EUV lithography is regarded as the most powerful candidate for patterning. So It has being studied to overcome the several issues such as source power for high throughput to apply volume production, mask defectivity from mask blank, RLS (Resolution, LWR & Sensitivity) trade off, which is the intrinsic property of EUV resist, and so on. For 2x nm node DRAM, dense contact hole, which has 3x nm half pitch (hp), has been issued to be made so far. There are two well-known methods for pattering; hole double patterning with ArF immersion lithography and single patterning with EUV lithography. EUV is more simple solution than hole double patterning for 3xnm hp dense contact hole, if it has large process window and comparable CD uniformity. Fortunately, EUV process already has larger process window than that of ArF immersion because its k1 value is a little bit high. But CD (critical dimension) uniformity and pattern profile were very poor in our initial result. Therefore it needs a lot of efforts to improve and compete against double patterning. The double patterning performance for 3xnm hp contact hole has been shown last year. In this paper, we will investigate on improving CD uniformity and pattern profile for 3x nm hp contact hole with several methods. Finally, the performance of EUV, which is achieved by our experiments, is being compared with that of double patterning in terms of CD uniformity and pattern profile.

Feasibility of EUVL thin absorber mask for minimization of mask shadowing effect

Conventional EVUL mask has 80nm absorber height which brings considerable shadowing effect. H-V CD bias of 40nm line and space by shadowing effect is more than 4nm, and that is expected to increase much more for narrower patterns by simulation. However various reports have been presented on mask shadowing bias correction, experimental results are not reliable to derive required mask bias correctly. Even more difficulty will arise when complex 2D structures are taken into account. Therefore minimization of shadowing effect by reducing absorber thickness is desirable. To transfer EUV lithography from experimental stage to HVM era, we need to find optimum absorber height of EUVL mask which allows us less shadowing effect with minimum loss of process window. In this paper, we present optimal absorber height of EUV mask which has been found in terms of shadowing effect and process window by simulation and exposure. To find minimized absorber height experimentally, we will compare the printing result of conventional and thin mask stack using simple 1:1 line and space and island patterns. Simulated H-V CD bias and process window will be presented.

EUV-patterning characterization using a 3D mask simulation and field EUV scanner

In the field of lithography technology, EUV lithography can be a leading candidate for sub-30 nm technology node. EUVL expose system has different characteristics compared to DUV exposure system. EUV source wavelength is short and no material is transparent to the source. So off-axis reflective optic system is used for patterning in place of on-axis refractive system of DUV system. And different reticle design is needed that consists of 40 pair of Mo/Si multi layer and absorber layer in place of conventional mask. Because of the oblique incidence on the mask, shadowing effect is occurred such as pattern asymmetry, shift and pattern bias depending on pattern orientation. For non-telecentric characteristics of EUV scanner, shadowing effect produces CD variation versus field position[1][2]. Besides, it is well known that EUV scanner has bigger flare than conventional DUV scanner. Therefore, the correction of mask shadowing effect and flare level are one of the important issues for EUV lithography. In this paper, process window and MEF of EUV lithography has been examined by 3D mask simulation. CD variation by shadowing is simulated for various pattern orientations. A shadowing correction method has been calculated due to field position to reduce shadowing effect. And the correction effect is examined by simulation and Experimental results. Principle of radial overlay shift due to field position is verified then the shift length of line and space pattern is calculated.

Study on the reduction of defects in immersion lithography

ArF Immersion lithography is expected to be a production-worthy technology for sub-60nm DRAM. It gives wider process window and better CD uniformity at the cost of defects and overlay accuracy. It is generally mentioned that immersion defects are generated during exposure and removed through pre-soak and post-soak process. A lot of efforts are being made towards less defect generation during exposure and more defect removal through pre-soak and postsoak process. We have experienced a variety of immersion defects and classified them into four types: bubble defect, water mark defect (T-top & Stain), swelling defect and bridge defect (Macro & Micro). We have worked very hard to reduce each immersion defects with immersion exposure and system. In this paper, we investigate method to reduce each immersion defects: bubble, water mark, swelling and bridge through our experiment.

Gate-first high-k/metal gate DRAM technology for low power and high performance products

It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was used on cell bit-line scheme, and single work function metal gate was employed without strain technology. The threshold voltage was controlled by using single TiN metal gate with La2O3 and SiGe/Si epi technology. The optimized DRAM high-k/metal gate peripheral transistors showed current gains of 65%/55% and DIBL improvements of 52%/46% for nMOSFET and pMOSFET, respectively. The results in process yield, performance, and reliability characteristics of the technology on 4Gb DRAM have shown that the gate-first high-k/metal gate DRAM technology can be regarded as one of the major candidates for next-generation low power DRAM products.

Improvement of alignment and overlay accuracy on amorphous carbon layers

ArF lithography has shrunk photo resist patterns down to 60nm from 80nm with the help of various RETs (resolution enhancement technologies). Photo resist thickness also has been thinner than ever to increase image contrast and DoF margin and to avoid pattern collapse due to high aspect ratio. Etching process became more difficult and marginal by using thin resist patterning so that new BARC materials having high etching selectivity are required. Since amorphous carbon (a-C) and SiON have good etch selectivity between them, they can be used as hard mask materials for thin resist process. Lithographic alignment system usually uses the light of 400 to 700nm. In general a-C has certain level of light absorption in this wavelength range and the absorption coefficient increases with deposition temperature of a-C. Because a-C film is not suitably transparent to the alignment light, overlay control might get worsen as the thickness of a-Carbon film increased. In this paper, we will present the effect of the thickness of a-Carbon film on alignment signal strength, alignment accuracy and overlay control of various layers. Simulation of alignment signal is conducted and compared with experiment results. It is also studied whether the overlay control can be improved by changing the spectrum of alignment light or structural design of alignment marks. Improvements on alignment accuracy and overlay control are examined by lowering the extinction coefficient, k of a-Carbon film. In conclusion, because photo resist only is not sufficient for a mask during etch step as the thickness decreased further, adoption of new hard mask is inevitable. It is the alignment trouble for a-Carbon that should be cleared before being named as a main stream of new hard mask.

Comparison between ADT and PPT for 2X DRAM patterning

Extreme Ultra-Violet (EUV) lithography is almost only solution reachable for next-generation lithography below 30nm half pitch with relative cost competitiveness. In this study, we investigate the feasibility of EUV lithography for applying 2X nm dynamic random access memory (DRAM) patterning. Very short wavelength of 13.5nm adds much more complexity to the lithography process. To understand for challenges of EUV lithography for high volume manufacturing (HVM), we study some EUV specific issues by using EUV full-field scanners, alpha demo tool (ADT) at IMEC and pre-production tool (PPT) at ASML. Good pattern fidelity of 2X nm node DRAM has been achieved by EUV ADT, such as dense line and dense contact-hole. In this paper, we report on EUV PPT performance such as resolution limit, MEEF, across slit CD uniformity (CDU) and focus & exposure latitude margin with 2X nm node DRAM layers in comparison with ADT performance. Due to less flare and aberration of PPT, we have expected that PPT shows good performance.

Topcoat-less resist process for 2Xnm node devices

In recent years ArF immersion lithography in memory devices, topcoat process has become baseline process in mass production in spite of its additional process steps and high cost-of-ownership. In order to overcome low process efficiency of topcoat process, high throughput scanner with higher scan speed and advanced rinse modules for decreasing defectivity are under development. Topcoat-less resist is also upgraded gradually which contains hydrophobic additives enables the extreme patterning without topcoat and high speed scanning. But current topcoat-less process has not matured yet for the dark-field mask compared to bright-field because of the blob defect in unexposed area. To minimizing blob defect level both material and process sequence should be optimized effectively. The authors have focused on blob defect and litho performance of topcoat-less resist process for dark field application in 2Xnm node devices.