T. Chiarella

Deposition of HfO2 on germanium and the impact of surface pretreatments

The deposition behavior of HfO2 by metalorganic chemical vapor deposition on germanium has been investigated. HfO2 films can be deposited on Ge with equally good quality as compared to high-k growth on silicon. Surface preparation is very important: compared to an HF-last, NH3 pretreatments result in smoother films with strongly reduced diffusion of germanium in the HfO2 film, resulting in a much better electrical performance. We clearly show that much thinner interfacial layers can be obtained, approximately half the thickness of what is typically found for depositions on silicon, suggesting the possibility of more aggressive equivalent oxide thickness∕leakage scaling.

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.

3D-carrier profiling in FinFETs using scanning spreading resistance microscopy

In this work, we demonstrate for the first time 3D-carrier profiling in FinFETs with nm-spatial resolution using SSRM. The results provide information on gate underlap, dopant conformality, source/drain doping profiles. The 3D-carrier profiles as extracted for two different device approaches (extensions vs. extension-less) are conclusive in demonstrating the differences in device performance and are consistent with first order 3D-simulations.

Phosphorus doped SiC Source Drain and SiGe channel for scaled bulk FinFETs

A P-SiC (Phosphorus doped Si1-xCx) SD (Source Drain) was developed on bulk-Si based nMOS FinFETs (n-FinFETs). P-SiC epitaxial growth on SD provides strain to boost n-FinFET mobility and drive current. Combination of LA (Laser Anneal) and low temperature RTA recovers P-SiC and PSi (Phosphorus doped Si, Si1-xPx) strain. A SiGe clad channel on pMOS FinFETs (p-FinFETs) was investigated. Narrower Si fin and SiGe epitaxial growth on fins increase mobility and drive current, which is based on the same carrier transport mechanism as conventional phonon scattering without velocity overshoot around 14nm node.

High-mobility Si 1−x Ge x -channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths

This paper is the first to provide a comprehensive study on the layout dependence of scaled Si<inf>1−x</inf>Ge<inf>x</inf>-channel pFETs.

Low VT metal-gate/high-k nMOSFETs — PBTI dependence and V T Tune-ability on La/Dy-capping layer locations and Laser annealing conditions

This paper provides a comprehensive study of the abnormal PBTI behaviors recently observed in La/Dy-capped high-k films in low-VT nMOSFETs. We found that process details in thermal budget (or dielectric intermixing) and oxygen content of the metal trigger the onset of these abnormalities. The DeltaVT relaxation during the PBTI recovery period induced by bulk trapping/de-trapping is believed to be oxygen vacancies related, and can be suppressed either by reducing dielectric intermixing with lower laser anneal powers (La above or below HK), or by increasing the oxygen concentration, i.e., TaCNO metal electrode instead of TaCN (La above HK). Putting La below HK can result in a similar VT tune-ability with less thermal budget for intermixing with the IL (with superior PBTI), without loss of current drive-ability. We propose Ta2C/HK/LaO/IL + LLP anneals as an optimum nFETs stack configuration for practical CMOS integration.

Electrical Characteristics of p-Type Bulk Si Fin Field-Effect Transistor Using Solid-Source Doping With 1-nm Phosphosilicate Glass

For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type (100) Si substrate was analyzed by secondary ion mass spectrometry and it was diffused deeper with higher thermal budget of anneal. Fabricated bulk Si FinFETs with using 1-nm phosphosilicate glass showed threshold voltage shift with several anneals at 1-μm and 70-nm gate lengths. Hole mobility at 1-μm gate length and transconductance at 70-nm gate length were also reduced due to increase in impurity concentration of phosphorus diffused by anneals into Fins. Phosphorus diffusion into Fins with using 1-nm phosphosilicate glass was investigated and phosphorus behavior after anneal was clarified by electrical data of p-type bulk Si FinFETs.

Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors

Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type FinFETs and p-type Si1-xGex-channel pFETs, and relies mainly on TCAD results. It will be shown that on n-FinFETs, tensile stressed Contact EtchStop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. Tensile stressed gates are shown to be an effective stressor on gatefirst n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. For pFETs with strained Si1-xGex-channels like the Implant-Free Quantum Well (IFQW) FET, it will be shown that elastic relaxation during source/drain recess is an important factor that reduces the effectiveness of Si1-yGey source/drain stressors. For scaled technologies, omitting the source/drain recess altogether and opting for a raised source/drain scheme is preferred. In IFQW pFETs, dependence of the drive current on transistor width is an important concern. It will be shown that a Si1-yGey source/drain reduces the layout dependence of IFQW FETs, an effect that is enhanced further when combined with a gate-last integration scheme.

Poly-Silicon Etch with Diluted Ammonia: Application to Replacement Gate Integration Scheme

With the continuous down scaling features sizes, the need of speed increase and power consumption reduction start to be more and more critical. The classical integration scheme of poly silicon gate on CMOS devices does not meet the requirements of the 45 nm technology node and beyond. On this matter, new materials and different integration flows are being investigated in order to improve the device performance. High-k materials associated with metals are actively investigated as new gate materials in which different integration approaches like metal gate first or metal gate last are proposed [1].

Scanning spreading resistance microscopy for carrier profiling beyond 32nm node

With the continued scaling of CMOS devices down to 32nm node and beyond, device performance is very sensitive to the lateral diffusion mechanisms influencing the effective channel length. Tools are thus, required to measure with sufficient resolution and accuracy the carrier distribution. Scanning spreading resistance microscopy (SSRM) has evolved as a successful carrier-profiling technique with sub-nm resolution, less than 2 nm/decade gradient resolution and high dynamic range 1015 to 1021 cm-3. In this work, we present the approaches (methodology and special test structures) to obtain a 3D-carrier concentration map for FinFET-based devices. We also correlate the results obtained with SSRM for various process conditions and its implications on device performance.