Yukishige Saito

A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film

A novel dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film is described. It is based on a new finding that threshold voltage (V/sub th/) depends on the concentration of nitrogen in the TiNx gate electrode. We found that a V/sub th/ shift as high as -110 mV is controlled by low-energy nitrogen-ion implantation (N I/I) into the titanium nitride film. By using this technology only for nMOSFETs, dual-metal gate CMOS devices are fabricated with a CMOS-process compatibility. A low V/sub th/ is achieved for both n- and pMOSFETs by combining N I/I and a low-doped channel structure.

Low-resistance self-aligned Ti-silicide technology for sub-quarter micron CMOS devices

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-/spl mu/m CMOS devices with low-resistance and uniform TiSi/sub 2/ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi/sub 2/ films were achieved on all narrow, long n/sup +/ and p/sup +/ poly-Si and diffusion layers of 0.15-/spl mu/m CMOS devices. TiSi/sub 2/ films with a sheet resistance of 5 to 7 /spl Omega//sq were stably and uniformly formed on 0.15-/spl mu/m-wide n/sup +/ and p/sup +/ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi/sub 2/ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-/spl mu/m NMOSFETs and PMOSFETs with self-aligned TiSi/sub 2/ films.

A highly manufacturable low power and high speed HfSiO CMOS FET with dual poly-Si gate electrodes

For 90 nm node poly-Si gated MISFETs with HfSiO (1.8 nm) insulator, a nearly symmetrical set of Vths for NFET and PFET: (0.38 V and -0.46 V, respectively) have been realized for low power device operation. The key technology is the suppression of Vth instability in PFETs arising from oxidation of the poly-Si/HfSiO interface, combined with channel engineering for the PFET. Our poly-Si/HfSiO gate-stacked CMOSFETs realize low I/sub off/ (N/PFET: 4.8/3.6 pA//spl mu/m) and high I/sub on/ (N/PFET: 469/140 /spl mu/A//spl mu/m) at V/sub DD/=1.2 V. Further, for SRAM cell using this CMOS, normal operation has been achieved.

Highly scalable nonvolatile TiOx/TaSiOy solid-electrolyte crossbar switch integrated in local interconnect for low power reconfigurable logic

A fully logic-compatible, nonvolatile crossbar switch using a novel dual-layer TiOx/TaSiOy solid-electrolyte, “NanoBridge”, has been developed for the first time, which is scalable to 50 nm and beyond and keeps the extremely low ON-resistance of ≪100 Ω. A key breakthrough is the dual-layer solid-electrolyte, in which TiOx works as an oxygen absorber as well as a superior ionic conductor, thus improving the yield, ON/OFF resistance ratio (≫106) and cycling endurance (≫103). The highly scalable 4 × 4 crossbar switch composed of NanoBridge integrated in a local Cu interconnect of a standard CMOS is successfully configured without select transistors. The nonvolatile solid-electrolyte, crossbar switch is a promising switch element for low power and low cost reconfigurable logic.

Effect of bottom electrode of ReRAM with Ta 2 O 5 /TiO 2 stack on RTN and retention

The Effect of the bottom electrode of ReRAM with a Ta2O5/TiO2 stack on noise and retention was investigated. The current fluctuation due to complex random telegraph noise (RTN) resulted in errors in the read-out with multi-level operation. We clarified that the Ti diffusion into the TiO2 layer from the bottom electrode increased the trap density and thus degraded current stability. The increased density caused the minority bit in the reset state to fail under a high temperature stress. The use of a stack with a Ru or Pt electrode with controlled Ti diffusion resulted in low noise and high thermal stability (≫190°C).

A new approach for improving operating margin of unipolar ReRAM using local minimu m of reset voltage

We propose a new approach for improving the operating margin of Ta2O5/plasma oxidized TiO2 stacked unipolar ReRAM. It was found that the reset voltage (switching from low resistance state to high resistance state) can be minimized by using local minimum against the resistance of the low resistance state. In addition, weakening the plasma oxidation condition reduced the power consumption and the variation of reset voltage. Excellent operating margin and more than 105 switching cycle times was successfully demonstrated using the integrated device.

A novel W/TiNx metal gate CMOS technology using nitrogen-concentration-controlled TiNx film

A W/TiN metal gate CMOS technology is newly proposed using a nitrogen-concentration-controlled TiNx film. This is based on a new finding that the threshold voltage of a TiNx gate MOSFET depends on the nitrogen concentration in the TiNx film. The threshold voltage for the W/TiNx gate nMOSFETs is controlled by a low-energy nitrogen ion implantation into the TiN film. This technique using one additional mask is highly compatible with the conventional CMOS process.

A shallow trench isolation with SiN guard-ring for sub-quarter micron CMOS technologies

Shallow trench isolation (STI) technology is important to realize high-speed and high-packing-density CMOS-LSIs. A new SiN guard-ring on the upper edge of filled SiO/sub 2/ for steep-sidewall STI is proposed and evaluated to improve the reverse narrow channel effect and device reliability. Good isolation characteristics and sufficient improvement of the reverse narrow channel effect are achieved for STI with SiN guard-ring structure.

Reliable solid-electrolyte crossbar switch for programmable logic device

Solid-electrolyte crossbar switch (namely NanoBridge) with low programming current of 420µA and highly reliable ON state against pulsed-alternating current (AC) stress is demonstrated under practical operating conditions of a programmable logic device (PLD). The ON-state duration under a pulsed-AC stress is achieved >10 years at 150°C. The high reliability under AC originates from the fact that the stress induced by Cu+ ion migration at a negative bias is recovered by a positive bias. NanoBridge is applicable in a scaled-down, nonvolatile PLD for hp28 and beyond.

A 0.10-/spl mu/m CMOS device with a 40-nm gate sidewall and multilevel interconnects for system LSI

A 0.10 /spl mu/m CMOS device for system LSI was successfully integrated with a 40 nm gate sidewall (SW) using a local-channel structure, an offset spacer, highly-doped source/drain extensions (SDE), deep pocket implants, a shallow source/drain (S/D) with 7 /spl Omega///spl square/ CoSi/sub 2/ and four-level interconnects. Good drive current characteristics were observed as 618 and 295 /spl mu/A//spl mu/m at 1.5 V with lower off-currents of 0.75 and 0.22 nA//spl mu/m for n/pMOSFETs, respectively.