T. R. Assis

Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology

In this paper, the alpha-particle induced soft error rate of two flip-flops are investigated as a function of operating frequency between 80 MHz and 1.2 GHz. The two flip-flops-an unhardened D flip-flop and a hardened pseudo-DICE flip-flop were designed in a TSMC 40 nm bulk CMOS technology. The error rates of both flip-flops increase with frequency. Analyses show that an internal single-event transient based upset mechanism is responsible for the frequency dependence of the error rates.

The Contribution of Low-Energy Protons to the Total On-Orbit SEU Rate

Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.

Impact of technology scaling on the combinational logic soft error rate

Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that the combinational logic soft error rate (SER) per logic gate decreases with scaling. This rate of decrease for the logic SER with scaling, however, is not as high as that of the latch SER. As a result, the proportion of combinational logic soft errors at the chip level is shown to increase. Results suggest that alpha-particle logic SER of average sized circuits is about 20% of the latch SER at 20-nm node while it is only 10% at 40-nm at 500 MHz. Moreover, the frequency at which combinational logic SER exceeds latch SER decreases with scaling. Factors that influence logic soft error scaling trends, such as sensitive area, transient pulse-widths and latch characteristics, are estimated through simulations and soft-error rate predictions for future technology nodes are made.

Temperature dependence of soft-error rates for FF designs in 20-nm bulk planar and 16-nm bulk FinFET technologies

Alpha particle-induced flip-flop soft-error rates (SER) for 20-nm bulk planar and 16-nm bulk FinFET technologies are characterized over temperature with different supply voltages. Experimental results indicate that the 16-nm FinFET SER changes insignificantly with temperature while the 20-nm planar SER increases by ~2x over the same temperature range. 3D TCAD and circuit-level simulations show changes in single-event transient (SET) pulse width and logic gate delay are the controlling factors, with opposing influences on SER.

High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process

A novel pulsed-latch design using hysteresis that operates similarly to an edge-triggered flip-flop with improved SER performance is presented. Design was implemented along with standard D-flip-flop (D-FF) and DICE flip-flop in a 20 nm CMOS process. Alpha and Neutron SER test results indicate ~26× and ~3× better SER hardness respectively for the pulsed-hysteresis-latch compared to D-FF. The design also benefits from a 25% higher speed and has a low area overhead of ~8% over the D-FF. A typical processor utilizing the pulsed-hysteresis-latch design can benefit from a ~5× overall SER reduction which is shown to be better than targeted DICE-FF based hardening, both in terms of SER reduction and performance penalty.

Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology

Isotropic alpha particle single-event upsets (SEU) in flip-flops are characterized over temperature and voltage supply variations in a 20-nm bulk planar complementary metal-oxide semiconductor (CMOS) process. The decrease of the MOSFET drain current in saturation with respect to increased temperature and reduced supply voltage explains the increased SEU sensitivity of the flip-flop designs. Experimental SEU cross sections from isotropic Americium-241, 5.4-MeV alpha particle show irradiation increases by 30 × on average, and up to orders of magnitude, as a result of increased device temperature and reduced supply voltage.

Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors

With the emphasis on low-power design, achieving soft error reliability in combinational logic circuits is extremely challenging. In this work, a circuit partitioning technique is used to minimize dynamic power consumption and to mitigate combinational logic soft errors. This work shows that for certain circuits, reduction in both power and combinational logic soft errors is simultaneously achievable. This is accomplished by partitioning the circuit so that the effective soft error cross section decreases and idle sub-circuits can be disabled to save power. The proposed method was evaluated experimentally using a 4-bit comparator fabricated at the 20-nm bulk CMOS technology node. With the application of the proposed technique, the alpha particle logic error cross section decreases by 30% compared to a baseline conventional circuit design. Dynamic power reduction of up to 50% is also seen for example circuits.

Terrestrial SER characterization for nanoscale technologies: A comparative study

In this work, the efforts of an industry wide consortium to characterize the logic soft error rate of a multitude of combinational and sequential logic circuits across multiple technologies is reported. The basic intent of the approach was to bring together the designs and intellectual property of various semiconductor companies on a single technology platform to be tested and compared under the same experimental conditions. This ensures that the measured results are validated, comparable and benchmarked against other similar designs. More importantly, crucial findings associated with this collaborative effort are also outlined in this paper. Some of the key results include the fact that scaling has led to the steady decline of failure in time (FIT) rates for flip-flops as well as combinational logic circuits. Additionally, the improvement in the soft error resilience provided by redundant node flip-flops has reduced with technology miniaturization due to the effects of charge sharing and multiple node charge collection. In spite of this, however, at high frequencies, the combinational logic soft error rate is comparable to the soft error rate of typical flip-flops. The experimental results are complemented with modeling various soft error mechanisms that affect modern high speed logic circuits.

Angular Effects of Heavy-Ion Strikes on Single-Event Upset Response of Flip-Flop Designs in 16-nm Bulk FinFET Technology

Radiation particles are incident on an integrated circuit (IC) from all angles. For planar technologies, angular incidence increases the deposited charge in a given volume, resulting in higher collected charge at a node and more transistors collecting charge due to increased charge sharing. For FinFET technologies, the physical structure of a FinFET is very different from that of a planar transistor. As a result, deposited and collected charge at a node for angular incidences will be different from what has been published for planar technologies. 3D TCAD simulations and heavy-ion experiments were carried out to investigate the angular effects on flip-flop (FF) single-event upsets (SEU) at the 16-nm bulk FinFET technology. Results show different SEU cross-section trends for the FinFET technology compared to planar technologies. Results show increased upset probability and SEU cross-sections with increasing tilt angles, but those are reduced with increasing roll angles for low-LET heavy-ion incidence. The main reason for this behavior is posited to be variations in charge track length within active Si regions.

SE performance of a Schmitt-trigger-based D-flip-flop design in a 16-nm bulk FinFET CMOS process

A hardened flip-flop (FF) design using Schmitt-trigger circuits for improved soft-error (SE) performance is presented. The Schmitt-trigger-based DFF (STDFF) design along with conventional DFF in a 16-nm bulk FinFET CMOS process were tested using alpha particles, heavy-ions, proton, and neutron. The STDFF design shows ~162× improvement in the alpha SE cross-section, up to ~30× improvement in heavy-ion SE cross-section, and ~5× improvement in both proton and neutron failure in time (FIT) rates compared with conventional DFF at nominal supply voltage and room temperature. STDFF also outperformed DFF for SE cross-section over frequency (up to 1.3 GHz) and temperature (up to 125 °C) ranges of interest.